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公开(公告)号：US11933844B2
公开(公告)日：2024-03-19
申请号：US17330653
申请日：2021-05-26
发明人： Wilson Pradeep , Prakash Narayanan
IPC分类号： G01R31/3177 , G01R31/317 , G06F11/10 , G11C29/36 , G11C29/42 , G11C29/56
CPC分类号： G01R31/3177 , G01R31/31718 , G01R31/31724 , G06F11/1048 , G06F11/1068 , G11C29/36 , G11C29/42 , G11C29/56004 , G11C2029/3602 , G11C2029/5602
摘要： A test override circuit includes a memory that includes multiple memory instances. A path selector receives a control signal from automatic test pattern generator equipment (ATE) to control data access to data paths that are operatively coupled between the memory instances and a plurality of logic endpoints. The path selector generates an output signal that indicates which of the data paths is selected in response to the control signal. A gating circuit enables the selected data paths to be accessed by at least one of the plurality of logic endpoints in response to the output signal from the path selector.
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2.发明公开公开(公告)号：US20230194605A1
公开(公告)日：2023-06-22
申请号：US18113688
申请日：2023-02-24
IPC分类号： G01R31/3177 , G01R31/3185
CPC分类号： G01R31/3177 , G01R31/318547 , G01R31/318536
摘要： Electronic scan circuitry includes a decompressor (510), a plurality of scan chains (520.i) fed by the decompressor (510), a scan circuit (502, 504) coupled to the plurality of scan chains (520.i) to scan them in and out, a masking circuit (590) fed by the scan chains (520.i), and a scannable masking qualification circuit (550, 560, 580) coupled to the masking circuit (590), the masking qualification circuit (550, 560, 580) scannable by scan-in of bits by the decompressor (510) along with scan-in of the scan chains (520.i), and the scannable masking qualification circuit (550, 560, 580) operable to hold such scanned-in bits upon scan-out of the scan chains through the masking circuit (590). Other scan circuitry, processes, circuits, devices and systems are also disclosed.
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公开(公告)号：US20220091919A1
公开(公告)日：2022-03-24
申请号：US17543827
申请日：2021-12-07
IPC分类号： G06F11/07 , G01R31/317 , G01R31/3185 , G11C29/14 , G11C29/50 , G11C29/32 , G11C29/20 , G11C29/12 , G11C29/56
摘要： A circuit includes a dynamic core data register (DCDR) cell that includes a data register, a shift register and an output circuit to route the output state of the data register or the shift register to an output of the DCDR in response to an output control input. A clock gate having a gate control input controls clocking of the shift register in response to a first scan enable signal. An output control gate controls the output control input of the output circuit and controls which outputs from the data register or the shift register are transferred to the output of the output circuit in response to a second scan enable signal. The first scan enable signal and the second scan enable signal to enable a state transition of the shift register at the output of the DCDR.
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公开(公告)号：US11073553B2
公开(公告)日：2021-07-27
申请号：US16185629
申请日：2018-11-09
发明人： Wilson Pradeep , Prakash Narayanan
IPC分类号： G11C29/42 , G11C29/36 , G06F11/10 , G01R31/3177 , G01R31/317 , G11C29/56
摘要： A circuit includes a multipath memory having multiple cells and a plurality of sequence generators. Each sequence generator of the plurality of sequence generators drives one separate cell of the multiple cells via an automatic test pattern generator (ATPG) mode signal for each cell. The ATPG mode signal for each cell is configured via a sequence configuration input that controls a timing sequence to test each cell. The state of the ATPG mode signal of each cell selects whether test data or functional data is output from the respective cell.
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5.发明申请公开(公告)号：US20150285860A1
公开(公告)日：2015-10-08
申请号：US14743720
申请日：2015-06-18
IPC分类号： G01R31/3177
CPC分类号： G01R31/3177 , G01R31/318536 , G01R31/318547
摘要： Electronic scan circuitry includes a decompressor (510), a plurality of scan chains (520.i) fed by the decompressor (510), a scan circuit (502, 504) coupled to the plurality of scan chains (520.i) to scan them in and out, a masking circuit (590) fed by the scan chains (520.i), and a scannable masking qualification circuit (550, 560, 580) coupled to the masking circuit (590), the masking qualification circuit (550, 560, 580) scannable by scan-in of bits by the decompressor (510) along with scan-in of the scan chains (520.i), and the scannable masking qualification circuit (550, 560, 580) operable to hold such scanned-in bits upon scan-out of the scan chains through the masking circuit (590). Other scan circuitry, processes, circuits, devices and systems are also disclosed.
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公开(公告)号：US11921159B2
公开(公告)日：2024-03-05
申请号：US18113688
申请日：2023-02-24
IPC分类号： G01R31/00 , G01R31/3177 , G01R31/3185
CPC分类号： G01R31/3177 , G01R31/318536 , G01R31/318547
摘要： Electronic scan circuitry includes a decompressor (510), a plurality of scan chains (520.i) fed by the decompressor (510), a scan circuit (502, 504) coupled to the plurality of scan chains (520.i) to scan them in and out, a masking circuit (590) fed by the scan chains (520.i), and a scannable masking qualification circuit (550, 560, 580) coupled to the masking circuit (590), the masking qualification circuit (550, 560, 580) scannable by scan-in of bits by the decompressor (510) along with scan-in of the scan chains (520.i), and the scannable masking qualification circuit (550, 560, 580) operable to hold such scanned-in bits upon scan-out of the scan chains through the masking circuit (590). Other scan circuitry, processes, circuits, devices and systems are also disclosed.
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公开(公告)号：US11821945B2
公开(公告)日：2023-11-21
申请号：US17217391
申请日：2021-03-30
IPC分类号： G01R31/317 , G01R31/3185 , G01R31/3177
CPC分类号： G01R31/31713 , G01R31/3177 , G01R31/318536 , G01R31/318572
摘要： An integrated circuit, comprising functional circuitry and testing circuitry. A first set of pads is operable in a first state for communicating testing signals to the testing circuitry and operable in a second state for communicating input/output signals to the functional circuitry. A second set of pads, differing from the first set of pads, is operable in the second state for communicating testing signals to the testing circuitry for testing signals associated in the second state with the first set of pads.
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公开(公告)号：US20230152373A1
公开(公告)日：2023-05-18
申请号：US18155190
申请日：2023-01-17
发明人： Prakash Narayanan , Nikita Naresh
IPC分类号： G01R31/3177 , G01R31/317
CPC分类号： G01R31/3177 , G01R31/31724 , G01R31/31703
摘要： A system is provided that includes a memory configured to store test patterns. A first lockstep core and a second lockstep core are configured to receive the same set of test patterns. First scan outputs are generated from the first lockstep core, and second scan outputs are generated from the second lockstep core during a reset of the first lockstep core and the second lockstep core. A comparator can be coupled to the first lockstep core and the second lockstep core and is configured to compare the first scan outputs to the second scan outputs. The first and second lockstep cores can be initialized to a similar state if the first and second scan outputs are the same. The first and second lockstep cores can comprise non-resettable flip flops.
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公开(公告)号：US11300615B2
公开(公告)日：2022-04-12
申请号：US16220209
申请日：2018-12-14
IPC分类号： G01R31/3183 , G01R31/3185 , G01R31/3181 , G01R31/317
摘要： A circuit includes a test circuit in an integrated circuit to test signal timing of a logic circuit under test in the integrated circuit. The signal timing includes timing measurements to determine if an output of the logic circuit under test changes state in response to a clock signal. The test circuit includes a bit register that specifies which bits of the logic circuit under test are to be tested in response to the clock signal. A configuration register specifies a selected clock source setting from multiple clock source settings corresponding to a signal speed. The selected clock source is employed to perform the timing measurements of the specified bits of the bit register.
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公开(公告)号：US11209481B2
公开(公告)日：2021-12-28
申请号：US16217289
申请日：2018-12-12
IPC分类号： G01R31/317 , G01R31/3185 , G01R31/3193 , G01R31/3177
摘要： A system includes a multiple input signature register (MISR) to receive outputs from M different scan chains in response to N test patterns applied to test an integrated circuit. The MISR provides N test signatures for the integrated circuit based on the outputs of the M different scan chains generated in response to each of the N test patterns. Each of the scan chains holds one or more test data bits that represent behavior of the integrated circuit in response to each of the N test patterns. A shift register is loaded from an interface and holds one of N comparison signatures that is used to validate a respective one of the N test signatures generated according to a given one of the N test patterns. A comparator compares each of the N test signatures with a respective one of the N comparison signatures to determine a failure condition based on the comparison.
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