公开(公告)号：US20150285860A1

公开(公告)日：2015-10-08

申请号：US14743720

申请日：2015-06-18

Applicant: Texas Instruments Incorporated

Inventor： Prakash Narayanan ,  Arvind Jain ,  Sundarrajan Subramanian ,  Rubin A. Parekhji

IPC: G01R31/3177

CPC classification number: G01R31/3177 ,  G01R31/318536 ,  G01R31/318547

Abstract: Electronic scan circuitry includes a decompressor (510), a plurality of scan chains (520.i) fed by the decompressor (510), a scan circuit (502, 504) coupled to the plurality of scan chains (520.i) to scan them in and out, a masking circuit (590) fed by the scan chains (520.i), and a scannable masking qualification circuit (550, 560, 580) coupled to the masking circuit (590), the masking qualification circuit (550, 560, 580) scannable by scan-in of bits by the decompressor (510) along with scan-in of the scan chains (520.i), and the scannable masking qualification circuit (550, 560, 580) operable to hold such scanned-in bits upon scan-out of the scan chains through the masking circuit (590). Other scan circuitry, processes, circuits, devices and systems are also disclosed.

公开(公告)号：US20130246889A1

公开(公告)日：2013-09-19

申请号：US13860773

申请日：2013-04-11

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Sanjay Kumar ,  Amit Kumar Dutta ,  Rubin A. Parekhji ,  Srivaths Ravi

IPC: G06F11/10

CPC classification number: G06F11/1008 ,  G06F11/1052 ,  G11C8/06 ,  G11C8/16 ,  G11C29/42 ,  G11C2029/0411 ,  H03M13/19

Abstract: An electronic circuit (200) for use with an accessing circuit (110) that supplies a given address and a partial write data portion and also has dummy cycles. The electronic circuit (200) includes a memory circuit (230) accessible at addresses, an address buffer (410), a data buffer (440) coupled to the memory circuit (230), and a control circuit (246) operable in the dummy cycles to read data from the memory circuit (230) to the data buffer (440) from a next address location in the memory circuit (230) and to store that next address in the address buffer (410). The electronic circuit further includes a multiplexer (430), a comparing circuit (420) responsive to the given address and a stored address in the address buffer (410), to operate the multiplexer (430) to pass data from the data buffer (440) or to pass data from the memory circuit (230) instead; and a mixer circuit (450) operable to put the partial write data portion into the data taken from the selected one of the data buffer (440) or memory circuit (230). Other circuits, devices, systems, processes of operation and processes of manufacture are also disclosed.

Abstract translation: 一种与提供给定地址和部分写入数据部分并且还具有虚拟周期的访问电路（110）一起使用的电子电路（200）。 电子电路（200）包括可在地址处访问的存储器电路（230），地址缓冲器（410），耦合到存储器电路（230）的数据缓冲器（440）和可在虚拟器件中操作的控制电路 循环，从存储器电路（230）中的下一个地址位置将数据从存储器电路（230）读取到数据缓冲器（440），并将该下一个地址存储在地址缓冲器（410）中。 电子电路还包括多路复用器（430），响应给定地址的比较电路（420）和地址缓冲器（410）中存储的地址，以操作多路复用器（430）以从数据缓冲器（440）传送数据 ）或者从存储器电路（230）传递数据; 以及混合器电路（450），其可操作以将所述部分写入数据部分放入从所述数据缓冲器（440）或存储器电路（230）中选择的数据采集的数据中。 还公开了其它电路，设备，系统，操作过程和制造过程。

公开(公告)号：US11119152B2

公开(公告)日：2021-09-14

申请号：US16780119

申请日：2020-02-03

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Prakash Narayanan ,  Rubin A. Parekhji ,  Arvind Jain ,  Sundarrajan Subramanian

IPC: G06F11/00 ,  G01R31/3177 ,  G01R31/3185

Abstract: Electronic scan circuitry includes a decompressor (510), a plurality of scan chains (520.i) fed by the decompressor (510), a scan circuit (502, 504) coupled to the plurality of scan chains (520.i) to scan them in and out, a masking circuit (590) fed by the scan chains (520.i), and a scannable masking qualification circuit (550, 560, 580) coupled to the masking circuit (590), the masking qualification circuit (550, 560, 580) scannable by scan-in of bits by the decompressor (510) along with scan-in of the scan chains (520.i), and the scannable masking qualification circuit (550, 560, 580) operable to hold such scanned-in bits upon scan-out of the scan chains through the masking circuit (590). Other scan circuitry, processes, circuits, devices and systems are also disclosed.

公开(公告)号：US09229055B2

公开(公告)日：2016-01-05

申请号：US14743720

申请日：2015-06-18

Applicant: Texas Instruments Incorporated

Inventor： Prakash Narayanan ,  Arvind Jain ,  Sundarrajan Subramanian ,  Rubin A. Parekhji

IPC: G06F11/00 ,  G01R31/3177 ,  G01R31/3185

CPC classification number: G01R31/3177 ,  G01R31/318536 ,  G01R31/318547

Abstract: Electronic scan circuitry includes a decompressor (510), a plurality of scan chains (520.i) fed by the decompressor (510), a scan circuit (502, 504) coupled to the plurality of scan chains (520.i) to scan them in and out, a masking circuit (590) fed by the scan chains (520.i), and a scannable masking qualification circuit (550, 560, 580) coupled to the masking circuit (590), the masking qualification circuit (550, 560, 580) scannable by scan-in of bits by the decompressor (510) along with scan-in of the scan chains (520.i), and the scannable masking qualification circuit (550, 560, 580) operable to hold such scanned-in bits upon scan-out of the scan chains through the masking circuit (590). Other scan circuitry, processes, circuits, devices and systems are also disclosed.

Abstract translation: 电子扫描电路包括解压缩器（510），由解压缩器（510）馈送的多个扫描链（520.i），耦合到多个扫描链（520.i）以扫描的扫描电路（502,504） 由扫描链（520.i）馈送的掩蔽电路（590）和耦合到屏蔽电路（590）的可扫描屏蔽鉴定电路（550,560,580），屏蔽鉴定电路（550） ，560,580）以及扫描链（520.i）的扫描以及可扫描掩蔽鉴定电路（550,560,580）可扫描由解压缩器（510）的位的扫描，以及可扫描掩蔽鉴定电路（550,560,580） 通过屏蔽电路扫描扫描链（590）后扫描位。 还公开了其它扫描电路，处理，电路，装置和系统。

公开(公告)号：US20180210030A1

公开(公告)日：2018-07-26

申请号：US15925200

申请日：2018-03-19

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Prakash Narayanan ,  Rubin A. Parekhji ,  Arvind Jain ,  Sundarrajan Subramanian

IPC: G01R31/3177 ,  G01R31/3185

CPC classification number: G01R31/3177 ,  G01R31/318536 ,  G01R31/318547

Abstract: Electronic scan circuitry includes a decompressor (510), a plurality of scan chains (520.i) fed by the decompressor (510), a scan circuit (502, 504) coupled to the plurality of scan chains (520.i) to scan them in and out, a masking circuit (590) fed by the scan chains (520.i), and a scannable masking qualification circuit (550, 560, 580) coupled to the masking circuit (590), the masking qualification circuit (550, 560, 580) scannable by scan-in of bits by the decompressor (510) along with scan-in of the scan chains (520.i), and the scannable masking qualification circuit (550, 560, 580) operable to hold such scanned-in bits upon scan-out of the scan chains through the masking circuit (590). Other scan circuitry, processes, circuits, devices and systems are also disclosed.

公开(公告)号：US08671329B2

公开(公告)日：2014-03-11

申请号：US13860773

申请日：2013-04-11

Applicant: Texas Instruments Incorporated

Inventor： Sanjay Kumar ,  Amit Kumar Dutta ,  Rubin A. Parekhji ,  Srivaths Ravi

IPC: G11C29/00

CPC classification number: G06F11/1008 ,  G06F11/1052 ,  G11C8/06 ,  G11C8/16 ,  G11C29/42 ,  G11C2029/0411 ,  H03M13/19

Abstract: An electronic circuit (200) for use with an accessing circuit (110) that supplies a given address and a partial write data portion and also has dummy cycles. The electronic circuit (200) includes a memory circuit (230) accessible at addresses, an address buffer (410), a data buffer (440) coupled to the memory circuit (230), and a control circuit (246) operable in the dummy cycles to read data from the memory circuit (230) to the data buffer (440) from a next address location in the memory circuit (230) and to store that next address in the address buffer (410). The electronic circuit further includes a multiplexer (430), a comparing circuit (420) responsive to the given address and a stored address in the address buffer (410), to operate the multiplexer (430) to pass data from the data buffer (440) or to pass data from the memory circuit (230) instead; and a mixer circuit (450) operable to put the partial write data portion into the data taken from the selected one of the data buffer (440) or memory circuit (230). Other circuits, devices, systems, processes of operation and processes of manufacture are also disclosed.

Abstract translation: 一种与提供给定地址和部分写入数据部分并且还具有虚拟周期的访问电路（110）一起使用的电子电路（200）。 电子电路（200）包括可在地址处访问的存储器电路（230），地址缓冲器（410），耦合到存储器电路（230）的数据缓冲器（440）和可在虚拟器件中操作的控制电路 循环，从存储器电路（230）中的下一个地址位置将数据从存储器电路（230）读取到数据缓冲器（440），并将该下一个地址存储在地址缓冲器（410）中。 电子电路还包括多路复用器（430），响应给定地址的比较电路（420）和地址缓冲器（410）中存储的地址，以操作多路复用器（430）以从数据缓冲器（440）传送数据 ）或者从存储器电路（230）传递数据; 以及混合器电路（450），其可操作以将所述部分写入数据部分放入从所述数据缓冲器（440）或存储器电路（230）中选择的数据采集的数据中。 还公开了其它电路，设备，系统，操作过程和制造过程。

公开(公告)号：US20250085346A1

公开(公告)日：2025-03-13

申请号：US18828799

申请日：2024-09-09

Applicant: Texas Instruments Incorporated

Inventor： Abhishek Chaudhary ,  Grant Ford ,  Rubin A. Parekhji ,  Edward C. Suder

IPC: G01R31/3185

Abstract: Methods and apparatus for boundary scan. In one example, a circuit includes at least one first input/output (I/O) device, at least one boundary scan element coupled to the at least one first I/O device, and at least one second I/O device coupled to the at least one boundary scan element. The circuit may further include a test controller coupled to the at least one boundary scan element and configured to control the at least one boundary scan element to drive the at least one first I/O device and the at least one second I/O device with a binary test signal.

公开(公告)号：US11921159B2

公开(公告)日：2024-03-05

申请号：US18113688

申请日：2023-02-24

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Prakash Narayanan ,  Rubin A. Parekhji ,  Arvind Jain ,  Sundarrajan Subramanian

IPC: G01R31/00 ,  G01R31/3177 ,  G01R31/3185

CPC classification number: G01R31/3177 ,  G01R31/318536 ,  G01R31/318547

Abstract: Electronic scan circuitry includes a decompressor (510), a plurality of scan chains (520.i) fed by the decompressor (510), a scan circuit (502, 504) coupled to the plurality of scan chains (520.i) to scan them in and out, a masking circuit (590) fed by the scan chains (520.i), and a scannable masking qualification circuit (550, 560, 580) coupled to the masking circuit (590), the masking qualification circuit (550, 560, 580) scannable by scan-in of bits by the decompressor (510) along with scan-in of the scan chains (520.i), and the scannable masking qualification circuit (550, 560, 580) operable to hold such scanned-in bits upon scan-out of the scan chains through the masking circuit (590). Other scan circuitry, processes, circuits, devices and systems are also disclosed.

公开(公告)号：US09581645B2

公开(公告)日：2017-02-28

申请号：US14179046

申请日：2014-02-12

Applicant: Texas Instruments Incorporated

Inventor： Adesh Sontakke ,  Rajesh Kumar Mittal ,  Rubin A. Parekhji ,  Upendra Narayan Tripathi

IPC: G01R31/319 ,  G01R31/14 ,  G01R31/317

CPC classification number: G01R31/31917 ,  G01R31/31716 ,  G01R31/31724

Abstract: A testable integrated circuit chip (80, 100) includes a functional circuit (80) having modules (IP.i), a storage circuit (110) operable to hold a table representing sets of compatible tests that are compatible for concurrence, and an on-chip test controller (140, 150) coupled with the storage circuit (110) and with the functional circuit modules (IP.i. The test controller (140, 150) is operable to dynamically schedule and trigger the tests in those sets, which promotes concurrent execution of tests in the functional circuit modules (IP.i). Other circuits, wireless chips, systems, and processes of operation and processes of manufacture are disclosed.

Abstract translation: 可测试的集成电路芯片（80,100）包括具有模块（IP.i）的功能电路（80），存储电路（110），其可操作以保持表示兼容兼容的兼容测试集合的表，以及on 芯片测试控制器（140,150）与存储电路（110）和功能电路模块（IP.i）耦合。测试控制器（140,150）可操作以动态地调度和触发那些组中的测试，其中 促进并行执行功能电路模块（IP.i）中的测试，公开了其他电路，无线芯片，系统以及操作过程和制造过程。

公开(公告)号：US20150006987A1

公开(公告)日：2015-01-01

申请号：US14487538

申请日：2014-09-16

Applicant: Texas Instruments Incorporated

Inventor： Prakash Narayanan ,  Arvind Jain ,  Sundarrajan Subramanian ,  Rubin A. Parekhji

IPC: G01R31/3185

CPC classification number: G01R31/3177 ,  G01R31/318536 ,  G01R31/318547

Abstract: Electronic scan circuitry includes a decompressor (510), a plurality of scan chains (520.i) fed by the decompressor (510), a scan circuit (502, 504) coupled to the plurality of scan chains (520.i) to scan them in and out, a masking circuit (590) fed by the scan chains (520.i), and a scannable masking qualification circuit (550, 560, 580) coupled to the masking circuit (590), the masking qualification circuit (550, 560, 580) scannable by scan-in of bits by the decompressor (510) along with scan-in of the scan chains (520.i), and the scannable masking qualification circuit (550, 560, 580) operable to hold such scanned-in bits upon scan-out of the scan chains through the masking circuit (590). Other scan circuitry, processes, circuits, devices and systems are also disclosed.

Abstract translation: 电子扫描电路包括解压缩器（510），由解压缩器（510）馈送的多个扫描链（520.i），耦合到多个扫描链（520.i）以扫描的扫描电路（502,504） 由扫描链（520.i）馈送的掩蔽电路（590）和耦合到屏蔽电路（590）的可扫描屏蔽鉴定电路（550,560,580），屏蔽鉴定电路（550） ，560,580）以及扫描链（520.i）的扫描以及可扫描掩蔽鉴定电路（550,560,580）可扫描由解压缩器（510）的位的扫描，以及可扫描掩蔽鉴定电路（550,560,580） 通过屏蔽电路扫描扫描链（590）后扫描位。 还公开了其它扫描电路，处理，电路，装置和系统。