公开(公告)号：US11387323B2

公开(公告)日：2022-07-12

申请号：US16931935

申请日：2020-07-17

Applicant: Texas Instruments Incorporated

Inventor： Chin-yu Tsai ,  Guruvayurappan Mathur

IPC: H01L29/10 ,  H01L27/092 ,  H01L29/45 ,  H01L29/78 ,  H01L21/265 ,  H01L21/8238 ,  H01L21/225 ,  H01L21/324 ,  H01L21/285 ,  H01L21/74 ,  H01L29/66 ,  H01L21/266

Abstract: An integrated circuit includes an extended drain MOS transistor. The substrate of the integrated circuit has a lower layer with a first conductivity type. A drain well of the extended drain MOS transistor has the first conductivity type. The drain well is separated from the lower layer by a drain isolation well having a second, opposite, conductivity type. A source region of the extended drain MOS transistor is separated from the lower layer by a body well having the second conductivity type. Both the drain isolation well and the body well contact the lower layer. An average dopant density of the second conductivity type in the drain isolation well is less than an average dopant density of the second conductivity type in the body well.

公开(公告)号：US10756187B1

公开(公告)日：2020-08-25

申请号：US16368102

申请日：2019-03-28

Applicant: Texas Instruments Incorporated

Inventor： Chin-yu Tsai ,  Guruvayurappan Mathur

IPC: H01L29/74 ,  H01L29/10 ,  H01L27/092 ,  H01L29/45 ,  H01L29/78 ,  H01L21/265 ,  H01L21/8238 ,  H01L21/225 ,  H01L21/324 ,  H01L21/285 ,  H01L21/74 ,  H01L29/66 ,  H01L21/266

Abstract: An integrated circuit includes an extended drain MOS transistor. The substrate of the integrated circuit has a lower layer with a first conductivity type. A drain well of the extended drain MOS transistor has the first conductivity type. The drain well is separated from the lower layer by a drain isolation well having a second, opposite, conductivity type. A source region of the extended drain MOS transistor is separated from the lower layer by a body well having the second conductivity type. Both the drain isolation well and the body well contact the lower layer. An average dopant density of the second conductivity type in the drain isolation well is less than an average dopant density of the second conductivity type in the body well.

公开(公告)号：US10700055B2

公开(公告)日：2020-06-30

申请号：US15838876

申请日：2017-12-12

Applicant: Texas Instruments Incorporated

Inventor： Akram Ali Salman ,  Guruvayurappan Mathur ,  Ryo Tsukahara

IPC: H01L27/02 ,  H01L27/06 ,  H01L29/08 ,  H01L29/66 ,  H01L29/73 ,  H01L29/06

Abstract: Disclosed examples provide fabrications methods and integrated circuits with back ballasted NPN bipolar transistors which include an n-type emitter in a P doped region, a p-type base with a first side facing the emitter, and an n-type collector laterally spaced from a second side of the base, where the collector includes a first side facing the second side of the base, an opposite second side, a silicided first collector portion and a silicide blocked second collector portion covered with a non-conductive dielectric that extends laterally between the first collector portion and the second side of the collector to provide back side ballasting for lateral breakdown and low current conduction via a deep N doped region while the vertical NPN turns on at a high voltage.

公开(公告)号：US10665663B1

公开(公告)日：2020-05-26

申请号：US16198527

申请日：2018-11-21

Applicant: Texas Instruments Incorporated

Inventor： Poornika Fernandes ,  Bhaskar Srinivasan ,  Guruvayurappan Mathur ,  Abbas Ali ,  David Matthew Curran ,  Neil L. Gardner

IPC: H01L29/00 ,  H01L49/02 ,  H01L27/06 ,  H01L21/02 ,  H01L21/762 ,  H01L21/285 ,  H01L21/3213

Abstract: An integrated circuit (IC) includes a semiconductor surface layer on a substrate including functional circuitry having circuit elements configured together with a metal-to-polysilicon capacitor on the semiconductor surface layer for realizing at least one circuit function. The metal-to-polysilicon capacitor includes a bottom plate including polysilicon, a capacitor dielectric including at least one capacitor dielectric layer on the bottom plate, a top plate on the capacitor dielectric, and contacts through a pre-metal dielectric layer that contact the top plate and contact the bottom plate. In lateral regions relative to the capacitor the capacitor dielectric layer has a thickness in a range between about 5% and about 50% of a thickness of the capacitor dielectric of the metal-to-polysilicon capacitor.