公开(公告)号：US20210288621A1

公开(公告)日：2021-09-16

申请号：US16817084

申请日：2020-03-12

Applicant: Texas Instruments Incorporated

Inventor： Ricky Dale Jordanger ,  Hector Torres

IPC: H03F3/387 ,  H03F3/45

Abstract: A current sense loop includes an attenuator circuit, which has an embedded input chopper circuit, and an amplifier circuit, which has an output chopper circuit. The embedded input chopper has a first chopper input that is coupled to a first attenuator input, a first chopper output that is coupled to a first attenuator output, a second chopper input that is coupled to a second attenuator input, and a second chopper output that is coupled to a second attenuator output. An amplifier has a first input coupled to the first attenuator output and a second input coupled to the second attenuator output. An NFET has a gate coupled to the amplifier output, a source coupled to a ground plane, and a drain coupled to the second attenuator input.

公开(公告)号：US20190393697A1

公开(公告)日：2019-12-26

申请号：US16132790

申请日：2018-09-17

Applicant: Texas Instruments Incorporated

Inventor： Ricky Dale Jordanger ,  Hector Torres

IPC: H02H9/00 ,  H03K17/687 ,  H02H9/02

Abstract: A slew-rate-control (SLC) circuit is coupled to an input for a driver circuit to provide a first binary value when the circuit is powered on and to control a slew rate when a pass element controlled by the driver circuit is enabled. The SLC circuit includes a capacitor node for coupling to a first terminal of an external capacitor, the capacitor node being coupled to the input. The SLC circuit also includes a SLC element coupled between the input and a first source of voltage to define the slew rate and a reset FET coupled between the input and a second source of voltage. The reset FET's gate is controlled by an over-current-protection signal that changes binary value when a short is detected. The reset FET is coupled to return the input to the first binary value responsive to detection of a short

公开(公告)号：US10062448B1

公开(公告)日：2018-08-28

申请号：US15805421

申请日：2017-11-07

Applicant: Texas Instruments Incorporated

Inventor： Hector Torres ,  Mark Bryan Hamlyn

IPC: G11C16/04 ,  G11C17/18 ,  G11C17/16 ,  G05F3/26

CPC classification number: G11C17/18 ,  G05F3/262 ,  G11C17/16

Abstract: A circuit includes a fuse cell with a current mirror. The first leg of the current minor includes first and second N-type transistors coupled in series between the upper and lower rails and the second leg includes third and fourth N-type transistors coupled in series between the upper and lower rails. The size of the first N-type transistor is (Y·A1), the second N-type transistor is (X·A2), the third N-type transistor is (X·A1) and the fourth N-type transistor is (Y·A2) where X and Y are integers and A1 and A2 are the sizes of respective reference transistors. A fuse has a first terminal coupled between the first and second N-type transistors and a second terminal coupled between the third and fourth N-type transistors; a first control node on the second leg of the current minor is coupled to control the voltage at an output node of the fuse cell.

公开(公告)号：US20140355161A1

公开(公告)日：2014-12-04

申请号：US13903736

申请日：2013-05-28

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Hector Torres ,  Charles Parkhurst

IPC: H02H9/02

CPC classification number: H02H9/02 ,  G05F1/5735 ,  G05F1/575 ,  H02H9/001

Abstract: Apparatus disclosed herein implement a fast transient precision current limiter such as may be included in an electronic voltage regulator. The current limiter includes two current sense element/current clamp control loops. A fast response time control loop first engages and clamps a current spike. A precision control loop then engages to more accurately clamp the output current to a programmed set point. The precision clamping loop includes an inner loop to linearize the precision current sense element. The inner loop forces the drain-to-source voltage (VDS) of the precision sense element to track the VDS of the regulator pass element. A more precise clamping operation results. Overall speed is not sacrificed as the fast response time clamping loop operates in parallel to protect circuitry while the precision clamping loop engages.

Abstract translation: 本文公开的装置实现快速瞬态精密限流器，例如可以包括在电子电压调节器中。 电流限制器包括两个电流检测元件/电流钳位控制回路。 快速响应时间控制回路首先接合并夹紧电流尖峰。 然后，精密控制回路接合以更精确地将输出电流钳位到编程的设定点。 精密钳位回路包括一个线性化精密电流检测元件的内环。 内部环路迫使精密检测元件的漏极 - 源极电压（VDS）跟踪调节器通过元件的VDS。 更精确的夹紧操作结果。 总体速度不会因为快速响应时间钳位回路并联运行而在精密钳位回路啮合时保护电路而牺牲。