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公开(公告)号:US10424361B2
公开(公告)日:2019-09-24
申请号:US15967511
申请日:2018-04-30
Applicant: Texas Instruments Incorporated
Inventor: John Anthony Rodriguez , Richard Allen Bailey
Abstract: A method of generating a random number from an electronic circuit memory and/or a system with the electronic circuit memory. The memory comprises a block of ferroelectric two transistor, two capacitor (2T-2C), memory cells. The method comprises: (i) first, writing a predetermined programming pattern to the block cells in a one transistor, one-capacitor (1T-1C) mode, thusly writing, per cell, a same data state to both a first and second sub-cell of the cell; (ii) second, reading the cells in a 2T-2C mode to generate a random number comprising a random bit from each of the cells; (iii) third, restoring the random number into the cells in a 2T-2C mode, thusly writing, per cell, a complementary data state to both a first and second sub-cell of the cell, responsive to a respective random number bit; and fourth, imprinting the random number in each cell in the block.
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公开(公告)号:US09824769B2
公开(公告)日:2017-11-21
申请号:US15146049
申请日:2016-05-04
Applicant: Texas Instruments Incorporated
Inventor: Sunil Kumar Dusa , Richard Allen Bailey , Archana Venugopal , John Anthony Rodriguez , Michael Allen Ball
CPC classification number: G11C17/18 , G11C17/165
Abstract: A fuse-programmable register or memory location having a plurality of fusible links of differing electrical characteristics in parallel. In one embodiment, three fusible links with different resistances are provided, such that application of a programming voltage non-uniformly distributes the current among the links, allowing varying voltages to selectively blow one or more of the links. Sensing of the programmed state is performed by applying a voltage across the parallel links and measuring the current in comparison with a plurality of reference currents. Reduction in the overhead chip area per bit and in the serial data communication latency are obtained.
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