公开(公告)号：US20230253060A1

公开(公告)日：2023-08-10

申请号：US18134239

申请日：2023-04-13

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Michael Allen Ball ,  Anand Seshadri

IPC: G11C17/16 ,  G11C17/18

CPC classification number: G11C17/165 ,  G11C17/18

Abstract: A re-programmable integrated circuit (IC) includes a plurality of non-volatile memory elements, each including a fuse portion initially configured to have either a first resistance value or a second resistance value. Re-programming circuitry includes a controllable element coupled to each fuse portion and selectively operable to cause an electrical current to flow through the fuse portion sufficient to cause that fuse portion to transition to an altered state having a resistance value greater than the first and second resistance values. Reference resistance circuitry is configurable between an initial state and a re-programmed state. Read circuitry determines the logic state of each of the memory elements using a comparator circuit operable to sense the resistance value of a fuse portion and the reference resistance, whether in the initial or re-programmed state, wherein the logic state of a memory element is a function of whether the resistance value of the fuse portion is greater than or less than the reference resistance.

公开(公告)号：US09824769B2

公开(公告)日：2017-11-21

申请号：US15146049

申请日：2016-05-04

Applicant: Texas Instruments Incorporated

Inventor： Sunil Kumar Dusa ,  Richard Allen Bailey ,  Archana Venugopal ,  John Anthony Rodriguez ,  Michael Allen Ball

IPC: G11C17/18 ,  G11C17/16

CPC classification number: G11C17/18 ,  G11C17/165

Abstract: A fuse-programmable register or memory location having a plurality of fusible links of differing electrical characteristics in parallel. In one embodiment, three fusible links with different resistances are provided, such that application of a programming voltage non-uniformly distributes the current among the links, allowing varying voltages to selectively blow one or more of the links. Sensing of the programmed state is performed by applying a voltage across the parallel links and measuring the current in comparison with a plurality of reference currents. Reduction in the overhead chip area per bit and in the serial data communication latency are obtained.

公开(公告)号：US20190207010A1

公开(公告)日：2019-07-04

申请号：US15859492

申请日：2017-12-30

Applicant: Texas Instruments Incorporated

Inventor： Binghua Hu ,  Michael Allen Ball ,  Jarvis Benjamin Jacobs ,  James Robert Todd

IPC: H01L29/66 ,  H01L21/265 ,  H01L29/167 ,  H01L21/8238 ,  H01L29/10 ,  H01L21/02 ,  H01L29/45 ,  H01L21/285 ,  H01L21/3213 ,  H01L21/762 ,  H01L29/417 ,  H01L29/06 ,  H01L29/08 ,  H01L27/092

CPC classification number: H01L29/665 ,  H01L21/02164 ,  H01L21/26513 ,  H01L21/28518 ,  H01L21/32137 ,  H01L21/76202 ,  H01L21/76224 ,  H01L21/823814 ,  H01L21/823871 ,  H01L21/823878 ,  H01L27/092 ,  H01L29/0649 ,  H01L29/0688 ,  H01L29/0847 ,  H01L29/1095 ,  H01L29/167 ,  H01L29/4175 ,  H01L29/456

Abstract: An integrated circuit having silicide block integrated with CMOS transistors is formed by forming a silicide block layer of primarily silicon dioxide, free of silicon nitride and silicon oxy-nitride, at less than 400° C. prior to annealing the PMOS sources and drains. A spike anneal process concurrently anneals the PMOS sources and drains and densifies the silicide block layer. The NMOS drain junctions are less than 120 nanometers; the NMOS halo regions include boron. The NMOS and PMOS transistors are laterally separated by an STI oxide layer. A wet deglaze process prior to metal silicide formation removes less than 25 percent of the silicide block layer, and exposes sides of the NMOS drains less than 20 percent of the drain junction depth. The metal silicide does not extend down the NMOS drains sides, directly adjacent to the STI oxide layer, more than 20 percent of the drain junction depth.

公开(公告)号：US20250006283A1

公开(公告)日：2025-01-02

申请号：US18883390

申请日：2024-09-12

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Michael Allen Ball ,  Anand Seshadri

IPC: G11C17/16 ,  G11C17/18

Abstract: A re-programmable integrated circuit (IC) includes a plurality of non-volatile memory elements, each including a fuse portion initially configured to have either a first resistance value or a second resistance value. Re-programming circuitry includes a controllable element coupled to each fuse portion and selectively operable to cause an electrical current to flow through the fuse portion sufficient to cause that fuse portion to transition to an altered state having a resistance value greater than the first and second resistance values. Reference resistance circuitry is configurable between an initial state and a re-programmed state. Read circuitry determines the logic state of each of the memory elements using a comparator circuit operable to sense the resistance value of a fuse portion and the reference resistance, whether in the initial or re-programmed state, wherein the logic state of a memory element is a function of whether the resistance value of the fuse portion is greater than or less than the reference resistance.

公开(公告)号：US11670390B2

公开(公告)日：2023-06-06

申请号：US17488008

申请日：2021-09-28

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Michael Allen Ball ,  Anand Seshadri

IPC: G11C17/18 ,  G11C17/16

CPC classification number: G11C17/165 ,  G11C17/18

Abstract: A re-programmable integrated circuit (IC) includes a plurality of non-volatile memory elements, each including a fuse portion initially configured to have either a first resistance value or a second resistance value. Re-programming circuitry includes a controllable element coupled to each fuse portion and selectively operable to cause an electrical current to flow through the fuse portion sufficient to cause that fuse portion to transition to an altered state having a resistance value greater than the first and second resistance values. Reference resistance circuitry is configurable between an initial state and a re-programmed state. Read circuitry determines the logic state of each of the memory elements using a comparator circuit operable to sense the resistance value of a fuse portion and the reference resistance, whether in the initial or re-programmed state, wherein the logic state of a memory element is a function of whether the resistance value of the fuse portion is greater than or less than the reference resistance.

公开(公告)号：US20230116065A1

公开(公告)日：2023-04-13

申请号：US17488008

申请日：2021-09-28

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Michael Allen Ball ,  Anand Seshadri

IPC: G11C17/16 ,  G11C17/18

Abstract: A re-programmable integrated circuit (IC) includes a plurality of non-volatile memory elements, each including a fuse portion initially configured to have either a first resistance value or a second resistance value. Re-programming circuitry includes a controllable element coupled to each fuse portion and selectively operable to cause an electrical current to flow through the fuse portion sufficient to cause that fuse portion to transition to an altered state having a resistance value greater than the first and second resistance values. Reference resistance circuitry is configurable between an initial state and a re-programmed state. Read circuity determines the logic state of each of the memory elements using a comparator circuit operable to sense the resistance value of a fuse portion and the reference resistance, whether in the initial or re-programmed state, wherein the logic state of a memory element is a function of whether the resistance value of the fuse portion is greater than or less than the reference resistance.

公开(公告)号：US10153053B2

公开(公告)日：2018-12-11

申请号：US15787905

申请日：2017-10-19

Applicant: Texas Instruments Incorporated

Inventor： Sunil Kumar Dusa ,  Richard Allen Bailey ,  Archana Venugopal ,  John Anthony Rodriguez ,  Michael Allen Ball

IPC: G11C17/18 ,  G11C17/16

Abstract: A fuse-programmable register or memory location having a plurality of fusible links of differing electrical characteristics in parallel. In one embodiment, three fusible links with different resistances are provided, such that application of a programming voltage non-uniformly distributes the current among the links, allowing varying voltages to selectively blow one or more of the links. Sensing of the programmed state is performed by applying a voltage across the parallel links and measuring the current in comparison with a plurality of reference currents. Reduction in the overhead chip area per bit and in the serial data communication latency are obtained.

公开(公告)号：US20180040381A1

公开(公告)日：2018-02-08

申请号：US15787905

申请日：2017-10-19

Applicant: Texas Instruments Incorporated

Inventor： Sunil Kumar Dusa ,  Richard Allen Bailey ,  Archana Venugopal ,  John Anthony Rodriguez ,  Michael Allen Ball

IPC: G11C17/18 ,  G11C17/16

CPC classification number: G11C17/18 ,  G11C17/165

Abstract: A fuse-programmable register or memory location having a plurality of fusible links of differing electrical characteristics in parallel. In one embodiment, three fusible links with different resistances are provided, such that application of a programming voltage non-uniformly distributes the current among the links, allowing varying voltages to selectively blow one or more of the links. Sensing of the programmed state is performed by applying a voltage across the parallel links and measuring the current in comparison with a plurality of reference currents. Reduction in the overhead chip area per bit and in the serial data communication latency are obtained.

公开(公告)号：US20170018311A1

公开(公告)日：2017-01-19

申请号：US15146049

申请日：2016-05-04

Applicant: Texas Instruments Incorporated

Inventor： Sunil Kumar Dusa ,  Richard Allen Bailey ,  Archana Venugopal ,  John Anthony Rodriguez ,  Michael Allen Ball

IPC: G11C17/18 ,  G11C17/16

CPC classification number: G11C17/18 ,  G11C17/165

Abstract: A fuse-programmable register or memory location having a plurality of fusible links of differing electrical characteristics in parallel. In one embodiment, three fusible links with different resistances are provided, such that application of a programming voltage non-uniformly distributes the current among the links, allowing varying voltages to selectively blow one or more of the links. Sensing of the programmed state is performed by applying a voltage across the parallel links and measuring the current in comparison with a plurality of reference currents. Reduction in the overhead chip area per bit and in the serial data communication latency are obtained.

Abstract translation: 熔丝可编程寄存器或存储器位置具有并联的具有不同电特性的多个可熔链路。 在一个实施例中，提供具有不同电阻的三个可熔链路，使得编程电压的施加不均匀地分布在链路之间的电流，允许变化的电压选择性地吹送一个或多个链路。 通过跨多个并联链路施加电压并且与多个参考电流相比测量电流来执行编程状态的感测。 获得每位开销芯片面积的减少和串行数据通信延迟。