公开(公告)号：US12150298B2

公开(公告)日：2024-11-19

申请号：US17515147

申请日：2021-10-29

Applicant: Texas Instruments Incorporated

Inventor： Anand Seshadri ,  Kemal Tamer San ,  Sunil Kumar Dusa ,  Michael Ball ,  Akram A. Salman

IPC: H01L21/00 ,  G11C17/16 ,  G11C17/18 ,  H01L23/525 ,  H10B20/20

Abstract: An integrated circuit (IC), comprising a fuse structure (eFuse) formed in a resistive layer over a semiconductor substrate, the eFuse subject to a change in resistance through the controlled application of a programming current from a programming voltage source connected to a first terminal of the eFuse; a blow transistor formed on or over the substrate and having a control terminal configured to cause the programming current to flow through the eFuse in response to a programming signal; an intermediate transistor formed on or over the substrate and electrically coupled in series between a second terminal of the eFuse and the blow transistor; and, control circuitry formed on or over the substrate and electrically coupled to a node between the second terminal of the eFuse and the intermediate transistor, the control circuitry configured to reduce the flow of programming current through the eFuse in the event that a voltage detected at the node reaches a threshold level.

公开(公告)号：US20230138308A1

公开(公告)日：2023-05-04

申请号：US17515147

申请日：2021-10-29

Applicant: Texas Instruments Incorporated

Inventor： Anand Seshadri ,  Kemal Tamer San ,  Sunil Kumar Dusa ,  Michael Ball ,  Akram A. Salman

IPC: H01L27/112 ,  H01L23/525 ,  G11C17/18 ,  G11C17/16

Abstract: An integrated circuit (IC), comprising a fuse structure (eFuse) formed in a resistive layer over a semiconductor substrate, the eFuse subject to a change in resistance through the controlled application of a programming current from a programming voltage source connected to a first terminal of the eFuse; a blow transistor formed on or over the substrate and having a control terminal configured to cause the programming current to flow through the eFuse in response to a programming signal; an intermediate transistor formed on or over the substrate and electrically coupled in series between a second terminal of the eFuse and the blow transistor; and, control circuitry formed on or over the substrate and electrically coupled to a node between the second terminal of the eFuse and the intermediate transistor, the control circuitry configured to reduce the flow of programming current through the eFuse in the event that a voltage detected at the node reaches a threshold level.

公开(公告)号：US09824769B2

公开(公告)日：2017-11-21

申请号：US15146049

申请日：2016-05-04

Applicant: Texas Instruments Incorporated

Inventor： Sunil Kumar Dusa ,  Richard Allen Bailey ,  Archana Venugopal ,  John Anthony Rodriguez ,  Michael Allen Ball

IPC: G11C17/18 ,  G11C17/16

CPC classification number: G11C17/18 ,  G11C17/165

Abstract: A fuse-programmable register or memory location having a plurality of fusible links of differing electrical characteristics in parallel. In one embodiment, three fusible links with different resistances are provided, such that application of a programming voltage non-uniformly distributes the current among the links, allowing varying voltages to selectively blow one or more of the links. Sensing of the programmed state is performed by applying a voltage across the parallel links and measuring the current in comparison with a plurality of reference currents. Reduction in the overhead chip area per bit and in the serial data communication latency are obtained.

公开(公告)号：US10153053B2

公开(公告)日：2018-12-11

申请号：US15787905

申请日：2017-10-19

Applicant: Texas Instruments Incorporated

Inventor： Sunil Kumar Dusa ,  Richard Allen Bailey ,  Archana Venugopal ,  John Anthony Rodriguez ,  Michael Allen Ball

IPC: G11C17/18 ,  G11C17/16

Abstract: A fuse-programmable register or memory location having a plurality of fusible links of differing electrical characteristics in parallel. In one embodiment, three fusible links with different resistances are provided, such that application of a programming voltage non-uniformly distributes the current among the links, allowing varying voltages to selectively blow one or more of the links. Sensing of the programmed state is performed by applying a voltage across the parallel links and measuring the current in comparison with a plurality of reference currents. Reduction in the overhead chip area per bit and in the serial data communication latency are obtained.

公开(公告)号：US20180040381A1

公开(公告)日：2018-02-08

申请号：US15787905

申请日：2017-10-19

Applicant: Texas Instruments Incorporated

Inventor： Sunil Kumar Dusa ,  Richard Allen Bailey ,  Archana Venugopal ,  John Anthony Rodriguez ,  Michael Allen Ball

IPC: G11C17/18 ,  G11C17/16

CPC classification number: G11C17/18 ,  G11C17/165

Abstract: A fuse-programmable register or memory location having a plurality of fusible links of differing electrical characteristics in parallel. In one embodiment, three fusible links with different resistances are provided, such that application of a programming voltage non-uniformly distributes the current among the links, allowing varying voltages to selectively blow one or more of the links. Sensing of the programmed state is performed by applying a voltage across the parallel links and measuring the current in comparison with a plurality of reference currents. Reduction in the overhead chip area per bit and in the serial data communication latency are obtained.

公开(公告)号：US20170018311A1

公开(公告)日：2017-01-19

申请号：US15146049

申请日：2016-05-04

Applicant: Texas Instruments Incorporated

Inventor： Sunil Kumar Dusa ,  Richard Allen Bailey ,  Archana Venugopal ,  John Anthony Rodriguez ,  Michael Allen Ball

IPC: G11C17/18 ,  G11C17/16

CPC classification number: G11C17/18 ,  G11C17/165

Abstract: A fuse-programmable register or memory location having a plurality of fusible links of differing electrical characteristics in parallel. In one embodiment, three fusible links with different resistances are provided, such that application of a programming voltage non-uniformly distributes the current among the links, allowing varying voltages to selectively blow one or more of the links. Sensing of the programmed state is performed by applying a voltage across the parallel links and measuring the current in comparison with a plurality of reference currents. Reduction in the overhead chip area per bit and in the serial data communication latency are obtained.

Abstract translation: 熔丝可编程寄存器或存储器位置具有并联的具有不同电特性的多个可熔链路。 在一个实施例中，提供具有不同电阻的三个可熔链路，使得编程电压的施加不均匀地分布在链路之间的电流，允许变化的电压选择性地吹送一个或多个链路。 通过跨多个并联链路施加电压并且与多个参考电流相比测量电流来执行编程状态的感测。 获得每位开销芯片面积的减少和串行数据通信延迟。