公开(公告)号：US11429125B1

公开(公告)日：2022-08-30

申请号：US17205155

申请日：2021-03-18

Applicant: Texas Instruments Incorporated

Inventor： Masahiro Yoshioka ,  Jeffrey David Johnson

IPC: G05F1/10 ,  G05F1/46 ,  H03K17/60 ,  H03M1/66

Abstract: A bandgap voltage reference circuit includes first and second transistors (e.g., 3-terminal BJTs or diode-connected BJTs), and a PTAT element (e.g., resistance or capacitance). The first transistor is at a first die location, and operates with a first base-emitter voltage. The second transistor is at a second die location, and operates with a second base-emitter voltage. Each of the first and second transistors may include multiple individual parallel-connected transistors. The PTAT element is operatively coupled to the first and second transistors such that a voltage difference between the first and second base-emitter voltages drops across the PTAT element. The first and second locations are separated by a distance (e.g., 1.5% or more of die length, or such that the respective centroids of the first and second transistor are spaced from one another). Such spatial distribution helps mitigate voltage shift induced by mechanical stress, and is insensitive to process variation.

公开(公告)号：US11133143B2

公开(公告)日：2021-09-28

申请号：US16585259

申请日：2019-09-27

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Masahiro Yoshioka ,  Muhammad Yusuf Ali ,  Kevin Ryan Duke

IPC: H03M1/06 ,  H01H83/04 ,  G05F1/56

Abstract: A two-wire current loop system includes a current loop with a transmitter and a host. The system also includes a monolithic integrated circuit included with the transmitter. The monolithic integrated circuit includes: 1) a power supply terminal coupled to the current loop; 2) a loop ground terminal coupled to the current loop and configured to output a current to the current loop; 3) device circuitry with a power supply node and an internal ground node, wherein the power supply node is coupled to the power supply terminal; and 4) a reverse wiring protection circuit coupled between the internal ground node of the device circuitry and the loop ground terminal.

公开(公告)号：US10177885B1

公开(公告)日：2019-01-08

申请号：US15794933

申请日：2017-10-26

Applicant: Texas Instruments Incorporated

Inventor： Masahiro Yoshioka ,  Michael Snedeker

IPC: H04L1/20 ,  H04L27/14

Abstract: In a carrier detector, the simple latch is replaced with a pulse timer and reference control module which outputs logic high (H) when more than two consecutive toggled signals come within 1.5 baud periods and keeps logic high (H) until it misses a toggled signal for two baud periods. This carrier detector has a tolerance for a false detection which happens when the frequency shifts from lower to higher and the input amplitude level does not reach a detectable level. With this transition, the amplitude level at filter output becomes higher due to the transient response of the filter and eventually this would trigger the comparator for only one baud period. The deglitch circuit, however, ignores this clock edge in the carrier detector as provided herein.