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公开(公告)号：US12289084B2
公开(公告)日：2025-04-29
申请号：US17588662
申请日：2022-01-31
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Masahiro Yoshioka , Gabriel Hernandez De La Cruz , Lawrence Cotton
Abstract: Examples of amplifier circuitry regulate a transconductance value (Gm) of operational transconductance amplifiers (OTAs) in the amplifier to be approximately the same, which value is based on a supply voltage and a reference voltage applied to a reference OTA and the internal resistance of the reference OTA. The reference OTA generates an output current based on Gm and the reference voltage, which current is compared to current generated by the supply voltage and internal resistance of the reference OTA. A tail current transistor of each of the reference OTA and a main OTA that mirrors the Gm of the reference OTA provide a tail current feedback path by which Gm is regulated. Amplifying circuitry is coupled to the main OTA to receive current signals. Based on the received current signals, amplifying circuitry generates a differential output voltage signal. The gain of the amplifying circuitry is proportional to the supply voltage and remains relatively constant across process temperature variations.
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公开(公告)号：US20230246612A1
公开(公告)日：2023-08-03
申请号：US17588662
申请日：2022-01-31
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Masahiro Yoshioka , Gabriel Hernandez De La Cruz , Lawrence Cotton
CPC classification number: H03F3/45183 , H03F1/301
Abstract: Examples of amplifier circuitry regulate a transconductance value (Gm) of operational transconductance amplifiers (OTAs) in the amplifier to be approximately the same, which value is based on a supply voltage and a reference voltage applied to a reference OTA and the internal resistance of the reference OTA. The reference OTA generates an output current based on Gm and the reference voltage, which current is compared to current generated by the supply voltage and internal resistance of the reference OTA. A tail current transistor of each of the reference OTA and a main OTA that mirrors the Gm of the reference OTA provide a tail current feedback path by which Gm is regulated. Amplifying circuitry is coupled to the main OTA to receive current signals. Based on the received current signals, amplifying circuitry generates a differential output voltage signal. The gain of the amplifying circuitry is proportional to the supply voltage and remains relatively constant across process temperature variations.
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公开(公告)号：US11546016B2
公开(公告)日：2023-01-03
申请号：US17205287
申请日：2021-03-18
Applicant: Texas Instruments Incorporated
Inventor： Masahiro Yoshioka , Michael Douglas Snedeker
Abstract: A communication system includes a first system input adapted to be coupled to a DC transient current transitioning between a starting level and a target level on a pseudo-sinusoidal path and incudes a second system input adapted to be coupled to a HART signal. The system includes an adder circuit having an output, a first adder input coupled to the first system input and a second adder input coupled to the second system input. The adder circuit provides a superimposed signal comprising the HART signal and the DC transient current.
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公开(公告)号：US20220302956A1
公开(公告)日：2022-09-22
申请号：US17205287
申请日：2021-03-18
Applicant: Texas Instruments Incorporated
Inventor： Masahiro Yoshioka , Michael Douglas Snedeker
Abstract: A communication system includes a first system input adapted to be coupled to a DC transient current transitioning between a starting level and a target level on a pseudo-sinusoidal path and incudes a second system input adapted to be coupled to a HART signal. The system includes an adder circuit having an output, a first adder input coupled to the first system input and a second adder input coupled to the second system input. The adder circuit provides a superimposed signal comprising the HART signal and the DC transient current.
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公开(公告)号：US10200163B1
公开(公告)日：2019-02-05
申请号：US15794933
申请日：2017-10-26
Applicant: Texas Instruments Incorporated
Inventor： Masahiro Yoshioka , Michael Snedeker
Abstract: In a carrier detector, the simple latch is replaced with a pulse timer and reference control module which outputs logic high (H) when more than two consecutive toggled signals come within 1.5 baud periods and keeps logic high (H) until it misses a toggled signal for two baud periods. This carrier detector has a tolerance for a false detection which happens when the frequency shifts from lower to higher and the input amplitude level does not reach a detectable level. With this transition, the amplitude level at filter output becomes higher due to the transient response of the filter and eventually this would trigger the comparator for only one baud period. The deglitch circuit, however, ignores this clock edge in the carrier detector as provided herein.
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Patent Agency Ranking
公开(公告)号：US11374483B2
公开(公告)日：2022-06-28
申请号：US17014881
申请日：2020-09-08
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Taisuke Kazama , Masahiro Yoshioka
Abstract: An apparatus includes a direct-current to direct-current (DC-DC) converter having an output terminal and at least one electronic switch. The DC-DC converter also includes: 1) a first feedback loop configured to control a voltage at the output terminal by adjusting a first switching parameter of the at least one electronic switch; and 2) a second feedback loop configured to adjust a second switching parameter of the at least one electronic switch. The second feedback loop includes a switched-capacitor circuit configured to determine a threshold signal based on an error between a reference signal and a control signal for the at least one electronic switch. The second feedback loop is configured to adjust the second switching parameter based on a comparison of an on-time signal with the threshold signal.
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公开(公告)号：US20220014403A1
公开(公告)日：2022-01-13
申请号：US17362480
申请日：2021-06-29
Applicant: Texas Instruments Incorporated
Inventor： Masahiro Yoshioka , Michael Douglas Snedeker
Abstract: An example apparatus includes: an input adapted to receive a signal modulated with data, counter circuitry coupled to the input and operable to determine a first count value in response to a first period between a first rising edge of the signal and a second rising edge of the signal, the first rising edge indicative of a start bit of the data, and determine a second count value based on a second period between a first falling edge of the signal and a second falling edge of the signal, data capture clock circuitry coupled to the counter circuitry and operable to generate a data capture clock based on the first count value in response to the second count value satisfying a threshold, and demodulator circuitry coupled to the counter circuitry and the data capture clock circuitry, the demodulator circuitry operable to generate a demodulated signal based on the data capture clock.
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公开(公告)号：US10770963B2
公开(公告)日：2020-09-08
申请号：US16175026
申请日：2018-10-30
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Taisuke Kazama , Masahiro Yoshioka
Abstract: An apparatus includes a direct-current to direct-current (DC-DC) converter having an output node and at least one electronic switch. The DC-DC converter also includes: 1) a first feedback loop configured to control a voltage at the output node by adjusting a first switching parameter of the at least one electronic switch; and 2) a second feedback loop configured to adjust a second switching parameter of the at least one electronic switch. The second feedback loop includes a switched-capacitor circuit configured to determine a threshold signal based on an error between a reference signal and a control signal for the at least one electronic switch. The second feedback loop is configured to adjust the second switching parameter based on a comparison of an on-time signal with the threshold signal.
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公开(公告)号：US11502884B2
公开(公告)日：2022-11-15
申请号：US17362480
申请日：2021-06-29
Applicant: Texas Instruments Incorporated
Inventor： Masahiro Yoshioka , Michael Douglas Snedeker
Abstract: An example apparatus includes: an input adapted to receive a signal modulated with data, counter circuitry coupled to the input and operable to determine a first count value in response to a first period between a first rising edge of the signal and a second rising edge of the signal, the first rising edge indicative of a start bit of the data, and determine a second count value based on a second period between a first falling edge of the signal and a second falling edge of the signal, data capture clock circuitry coupled to the counter circuitry and operable to generate a data capture clock based on the first count value in response to the second count value satisfying a threshold, and demodulator circuitry coupled to the counter circuitry and the data capture clock circuitry, the demodulator circuitry operable to generate a demodulated signal based on the data capture clock.
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10.发明申请公开(公告)号：US20220300016A1
公开(公告)日：2022-09-22
申请号：US17205155
申请日：2021-03-18
Applicant: Texas Instruments Incorporated
Inventor： Masahiro Yoshioka , Jeffrey David Johnson
Abstract: A bandgap voltage reference circuit includes first and second transistors (e.g., 3-terminal BJTs or diode-connected BJTs), and a PTAT element (e.g., resistance or capacitance). The first transistor is at a first die location, and operates with a first base-emitter voltage. The second transistor is at a second die location, and operates with a second base-emitter voltage. Each of the first and second transistors may include multiple individual parallel-connected transistors. The PTAT element is operatively coupled to the first and second transistors such that a voltage difference between the first and second base-emitter voltages drops across the PTAT element. The first and second locations are separated by a distance (e.g., 1.5% or more of die length, or such that the respective centroids of the first and second transistor are spaced from one another). Such spatial distribution helps mitigate voltage shift induced by mechanical stress, and is insensitive to process variation.
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