公开(公告)号：US20250080918A1

公开(公告)日：2025-03-06

申请号：US18240676

申请日：2023-08-31

Applicant: Texas Instruments Incorporated

Inventor： Bichoy Bahr ,  Udit Rawat ,  Mohit Chawla ,  Yogesh Ramadass

IPC: H04R17/02 ,  H04R17/10 ,  H10N30/063 ,  H10N30/086 ,  H10N30/20 ,  H10N30/87

Abstract: In one example, an apparatus comprises a substrate, a first piezoelectric flap, and a second piezoelectric flap. The substrate has an opening. The first piezoelectric flap has a first end on the substrate and has a first portion extending over a first part of the opening, the first piezoelectric flap including first electrodes, in which the first electrodes extend no more than half of a first length of the first portion. The second piezoelectric flap has a second end on the substrate and has a second portion extending over a second part of the opening, the second piezoelectric flap including second electrodes, in which the second electrodes extend no more than half of a second length of the second portion.

公开(公告)号：US11750992B2

公开(公告)日：2023-09-05

申请号：US17360270

申请日：2021-06-28

Applicant: Texas Instruments Incorporated

Inventor： Venkata Ramanan Ramamurthy ,  Mohit Chawla

IPC: H04R29/00 ,  G01R31/56 ,  H03F3/217

CPC classification number: H04R29/001 ,  G01R31/56 ,  H03F3/217 ,  H03F2200/03

Abstract: A switching amplifier includes: a driver circuit with differential inputs and differential outputs; and a fault detection circuit coupled to the differential outputs. The fault detection circuit includes: a power supply input; and a sense circuit coupled to the differential outputs. The sense circuit includes: a first resistor between the power supply input and a positive output of the differential outputs; a second resistor between the positive output and ground; a third resistor between the power supply input and a negative output of the differential outputs; and a fourth resistor between the negative output and ground. The fault detection circuit also includes an analyzer circuit coupled to the sense circuit and configured to determine a fault location relative to the differential outputs based on an output of the sense circuit.

公开(公告)号：US20220229457A1

公开(公告)日：2022-07-21

申请号：US17340506

申请日：2021-06-07

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Supriyo Palit ,  Mohit Chawla

IPC: G05F1/625 ,  H03G3/30 ,  H04R3/04 ,  H04R29/00 ,  H04S1/00

Abstract: A controller regulates the voltage delivered to the load and current drawn from the battery in an audio system depending on ripple in the battery voltage which is input to the controller to allocate power for audio playback. Regulation maximizes available headroom while avoiding audio clipping. The effect of internal battery and external parasitic resistance (ESR) on ripple is compensated by an iterative process. ESR is rapidly increased whenever the minimum of the battery voltage input to the controller falls below a clipping threshold and slowly decreased whenever such voltage exceeds such threshold and the audio is under compression. A limiter allocates power to utilize more of the available audio headroom. A de-emphasis filter in each audio signal path compensates for capacitive ripple in the battery voltage input to the controller. As the frequency of the audio input changes, the filter(s) allow frequency-dependent power/current regulation to fill the full audio range without distortion.

公开(公告)号：US20220021379A1

公开(公告)日：2022-01-20

申请号：US17364489

申请日：2021-06-30

Applicant: Texas Instruments Incorporated

Inventor： David Hernandez ,  David Patrick Magee ,  Mohit Chawla ,  James Kelly Griffin

IPC: H03K7/08

Abstract: Techniques are provided herein for generating PWM signals. Furthermore, a direct-drive method is disclosed in which a PWM signal is generated as a differential signal made up of OUTP and OUTN signals, where OUTP is a copy of OUTN but shifted in time by half a period. The PWM signal is generated by passing each of an input period and an input duty cycle through corresponding sigma-delta circuits to generate a refined period and a refined duty cycle, respectively. In some example cases, a threshold mapper uses a lookup table (LUT) or similar mechanism to select timing thresholds for rise times and fall times for each of the OUTP and OUTN signals, where the timing thresholds are selected based on the refined period and the refined duty cycle. In some example cases, a pulse generator generates the OUTP and OUTN signals based on the timing thresholds.

公开(公告)号：US10396779B2

公开(公告)日：2019-08-27

申请号：US15852132

申请日：2017-12-22

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Mohit Chawla

IPC: G01R19/25 ,  H03K17/687 ,  H03F3/217 ,  H03F3/185 ,  H04R29/00 ,  H03F1/26 ,  H03F1/32

Abstract: A circuit includes a pair of high side transistors, a pair of low side transistors, a first sense resistor coupled to one of the low side transistors at a first sense node, and a second sense resistor coupled to another of the low side transistors at a second sense node. The first and second sense resistors couple together at a ground node. The circuit includes a first switch network coupled to the first sense resistor, a second switch network coupled to the second sense resistor, a first pair of switches configured to selectively provide a potential of the ground node or a potential of the first sense node as a ground potential to the first switch network, and a second pair of switches configured to selectively provide the potential of the ground node or a potential of the second sense node as a ground potential to the second switch network.