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    COMPRESSED SCAN CHAIN DIAGNOSIS BY INTERNAL CHAIN OBSERVATION, PROCESSES, CIRCUITS, DEVICES AND SYSTEMS
    11.
    发明申请
    COMPRESSED SCAN CHAIN DIAGNOSIS BY INTERNAL CHAIN OBSERVATION, PROCESSES, CIRCUITS, DEVICES AND SYSTEMS 审中-公开

    公开(公告)号：US20200174069A1

    公开(公告)日：2020-06-04

    申请号：US16780119

    申请日：2020-02-03

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Prakash Narayanan ,  Rubin A. Parekhji ,  Arvind Jain ,  Sundarrajan Subramanian

    IPC: G01R31/3177 ,  G01R31/3185

    Abstract: Electronic scan circuitry includes a decompressor (510), a plurality of scan chains (520.i) fed by the decompressor (510), a scan circuit (502, 504) coupled to the plurality of scan chains (520.i) to scan them in and out, a masking circuit (590) fed by the scan chains (520.i), and a scannable masking qualification circuit (550, 560, 580) coupled to the masking circuit (590), the masking qualification circuit (550, 560, 580) scannable by scan-in of bits by the decompressor (510) along with scan-in of the scan chains (520.i), and the scannable masking qualification circuit (550, 560, 580) operable to hold such scanned-in bits upon scan-out of the scan chains through the masking circuit (590). Other scan circuitry, processes, circuits, devices and systems are also disclosed.

    Compressed scan chains with three input mask gates and registers
    12.
    发明授权
    Compressed scan chains with three input mask gates and registers 有权

    公开(公告)号：US10591540B2

    公开(公告)日：2020-03-17

    申请号：US15925200

    申请日：2018-03-19

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Prakash Narayanan ,  Rubin A. Parekhji ,  Arvind Jain ,  Sundarrajan Subramanian

    IPC: G06F11/00 ,  G01R31/3177 ,  G01R31/3185

    Abstract: Electronic scan circuitry includes a decompressor (510), a plurality of scan chains (520.i) fed by the decompressor (510), a scan circuit (502, 504) coupled to the plurality of scan chains (520.i) to scan them in and out, a masking circuit (590) fed by the scan chains (520.i), and a scannable masking qualification circuit (550, 560, 580) coupled to the masking circuit (590), the masking qualification circuit (550, 560, 580) scannable by scan-in of bits by the decompressor (510) along with scan-in of the scan chains (520.i), and the scannable masking qualification circuit (550, 560, 580) operable to hold such scanned-in bits upon scan-out of the scan chains through the masking circuit (590). Other scan circuitry, processes, circuits, devices and systems are also disclosed.

    Scan chain masking qualification circuit shift register and bit-field decoders
    15.
    发明授权
    Scan chain masking qualification circuit shift register and bit-field decoders 有权
    扫描链屏蔽鉴定电路移位寄存器和位字段解码器

    公开(公告)号：US09091729B2

    公开(公告)日：2015-07-28

    申请号：US14487538

    申请日：2014-09-16

    Applicant: Texas Instruments Incorporated

    Inventor： Prakash Narayanan ,  Arvind Jain ,  Sundarrajan Subramanian ,  Rubin A. Parekhji

    IPC: G06F11/00 ,  G01R31/3185

    CPC classification number: G01R31/3177 ,  G01R31/318536 ,  G01R31/318547

    Abstract: Electronic scan circuitry includes a decompressor (510), a plurality of scan chains (520.i) fed by the decompressor (510), a scan circuit (502, 504) coupled to the plurality of scan chains (520.i) to scan them in and out, a masking circuit (590) fed by the scan chains (520.i), and a scannable masking qualification circuit (550, 560, 580) coupled to the masking circuit (590), the masking qualification circuit (550, 560, 580) scannable by scan-in of bits by the decompressor (510) along with scan-in of the scan chains (520.i), and the scannable masking qualification circuit (550, 560, 580) operable to hold such scanned-in bits upon scan-out of the scan chains through the masking circuit (590). Other scan circuitry, processes, circuits, devices and systems are also disclosed.

    Abstract translation: 电子扫描电路包括解压缩器（510），由解压缩器（510）馈送的多个扫描链（520.i），耦合到多个扫描链（520.i）以扫描的扫描电路（502,504） 由扫描链（520.i）馈送的掩蔽电路（590）和耦合到屏蔽电路（590）的可扫描屏蔽鉴定电路（550,560,580），屏蔽鉴定电路（550） ，560,580）以及扫描链（520.i）的扫描以及可扫描掩蔽鉴定电路（550,560,580）可扫描由解压缩器（510）的位的扫描，以及可扫描掩蔽鉴定电路（550,560,580） 通过屏蔽电路扫描扫描链（590）后扫描位。 还公开了其它扫描电路，处理，电路，装置和系统。

    BUILT-IN SELF-TEST METHODS, CIRCUITS AND APPARATUS FOR CONCURRENT TEST OF RF MODULES WITH A DYNAMICALLY CONFIGURABLE TEST STRUCTURE
    16.
    发明申请
    BUILT-IN SELF-TEST METHODS, CIRCUITS AND APPARATUS FOR CONCURRENT TEST OF RF MODULES WITH A DYNAMICALLY CONFIGURABLE TEST STRUCTURE 审中-公开
    内置自测试方法，电路和装置，用于具有动态可配置的测试结构的RF模块的同时测试

    公开(公告)号：US20140232422A1

    公开(公告)日：2014-08-21

    申请号：US14179046

    申请日：2014-02-12

    Applicant: Texas Instruments Incorporated

    Inventor： Adesh Sontakke ,  Rajesh Kumar Mittal ,  Rubin A. Parekhji ,  Upendra Narayan Tripathi

    IPC: G01R31/319

    CPC classification number: G01R31/31917 ,  G01R31/31716 ,  G01R31/31724

    Abstract: A testable integrated circuit chip (80, 100) includes a functional circuit (80) having modules (IP.i), a storage circuit (110) operable to hold a table representing sets of compatible tests that are compatible for concurrence, and an on-chip test controller (140, 150) coupled with said storage circuit (110) and with said functional circuit modules (IP.i), said test controller (140, 150) operable to dynamically schedule and trigger the tests in those sets, whereby promoting concurrent execution of tests in said functional circuit modules (IP.i). Other circuits, wireless chips, systems, and processes of operation and processes of manufacture are disclosed.

    Abstract translation: 可测试的集成电路芯片（80,100）包括具有模块（IP.i）的功能电路（80），存储电路（110），其可操作以保持表示兼容兼容的兼容测试集合的表，以及on 与所述存储电路（110）和所述功能电路模块（IP.i）耦合的芯片测试控制器（140,150），所述测试控制器（140,150）可操作以动态地调度和触发这些组中的测试，由此 促进在所述功能电路模块（IP.i）中并行执行测试。 公开了其他电路，无线芯片，系统以及操作过程和制造过程。

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