公开(公告)号：US20190245541A1

公开(公告)日：2019-08-08

申请号：US16388353

申请日：2019-04-18

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Xiong Li ,  Toru Tanaka

IPC: H03K19/0952 ,  H03K5/19 ,  H03K19/017 ,  H02M7/5387 ,  H03K17/22 ,  H02M7/537 ,  H03K17/06

CPC classification number: H03K19/0952 ,  H02M7/537 ,  H02M7/53873 ,  H03K5/19 ,  H03K17/063 ,  H03K17/223 ,  H03K19/01707

Abstract: A gate driver includes a drive signal input terminal, a drive signal output terminal, a gate drive circuit, and a serial communication interface. The drive signal input terminal is configured to receive a gate drive signal. The gate drive circuit is coupled to the drive signal input terminal and the drive signal output terminal. The gate drive circuit is configured to provide the gate drive signal to the drive signal output terminal. The serial communication interface is coupled to the drive signal input terminal.

公开(公告)号：US10291163B2

公开(公告)日：2019-05-14

申请号：US15142219

申请日：2016-04-29

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Alejandro Vera ,  Shyamsunder Balasubramanian ,  Toshio Yamanaka ,  Toru Tanaka

IPC: H02P8/12 ,  G05F1/595

Abstract: A voltage regulator includes an output transistor, an error amplifier coupled to the output transistor, a cascode transistor coupled to the output transistor in series, and a cascode bias circuit coupled to the cascode transistor and the output transistor. The output transistor is configured to generate an output signal at a first voltage. The error amplifier is configured to receive a reference signal. The cascode bias circuit is configured to bias the cascode transistor such that, in response to a drain-to-source short circuit of the output transistor, the cascode transistor generates the output signal at the first voltage.

公开(公告)号：US10312914B2

公开(公告)日：2019-06-04

申请号：US15854515

申请日：2017-12-26

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Xiong Li ,  Toru Tanaka

IPC: H03K19/0952 ,  H02M7/537 ,  H03K19/017 ,  H03K17/22 ,  H03K5/19 ,  H03K17/06

Abstract: A gate driver includes a drive signal input terminal, a drive signal output terminal, a gate drive circuit, and a serial communication interface. The drive signal input terminal is configured to receive a gate drive signal. The gate drive circuit is coupled to the drive signal input terminal and the drive signal output terminal. The gate drive circuit is configured to provide the gate drive signal to the drive signal output terminal. The serial communication interface is coupled to the drive signal input terminal.