中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

14 records (took 0.017 seconds)

    WELDING-TYPE FIXING CAP AND CELL MODULE EQUIPPED WITH THE SAME
    12.
    发明申请
    WELDING-TYPE FIXING CAP AND CELL MODULE EQUIPPED WITH THE SAME 审中-公开
    焊接型固定盖和与其配套的电池模块

    公开(公告)号：US20080187827A1

    公开(公告)日：2008-08-07

    申请号：US11951231

    申请日：2007-12-05

    Applicant: Tae-yong Kim ,  Dae-won Han

    Inventor： Tae-yong Kim ,  Dae-won Han

    IPC: H01M2/04 ,  H01M6/42

    CPC classification number: H01M2/105 ,  H01M2/023 ,  H01M2/0426 ,  H01M2/043 ,  H01M2/06 ,  H01M2/12

    Abstract: Disclosed is a welding-type fixing cap used for attachment to both ends of a cylindrical battery composed of metal materials. The welding-type fixing cap comprises a ring-shaped side wall; a visor surface extending outwards from one end of the side wall; a welding lug formed on the visor surface, wherein the welding lug is meltable in a welding process; a cutting hole formed in the side wall, wherein the cutting hole is dimensioned and configured for discharging gas. The welding lug is positioned distal to the side wall and proximal to a cutting hole. The welding-type fixing cap has a sufficient strength, while recuding electric current leakage during a contact-resistance welding.

    Abstract translation: 公开了一种用于连接到由金属材料构成的圆柱形电池的两端的焊接型固定帽。 焊接型固定帽包括环形侧壁; 从侧壁的一端向外延伸的面板表面; 焊接凸耳，其形成在所述面板表面上，其中所述焊接凸耳在焊接过程中是可熔化的; 形成在所述侧壁中的切割孔，其中所述切割孔的尺寸被设计成用于排出气体。 焊接凸缘位于侧壁的远侧并且靠近切割孔。 焊接型固定盖具有足够的强度，同时在接触电阻焊接期间消除电流泄漏。

    SERIAL INTERFACE BETWEEN UNIT CELLS
    13.
    发明申请
    SERIAL INTERFACE BETWEEN UNIT CELLS 有权
    单元间的串行接口

    公开(公告)号：US20080182160A1

    公开(公告)日：2008-07-31

    申请号：US12017290

    申请日：2008-01-21

    Applicant: Tae-yong Kim ,  Zin Park ,  Seung-il Kim

    Inventor： Tae-yong Kim ,  Zin Park ,  Seung-il Kim

    IPC: H01M2/12

    CPC classification number: H01M2/12 ,  H01M2/204 ,  H01M10/613 ,  H01M10/643 ,  H01M10/6562

    Abstract: A serial interface interposed between two serially connected unit cells provides mechanical strength to the serial connection and conductive coupling therebetween. The serial interface includes an inter-connector having a first vent hole formed therein configured for conductively coupling an anode outer wall of a first unit cell and a cathode terminal of a second unit cell to each other; and a spacer having a second vent hole formed therein and configured to be disposed between the inter-connector and an anode outer wall of the second unit cell to prevent a short-circuit due to the movement of the inter-connector.

    Abstract translation: 插入在两个串联连接的单元电池之间的串行接口为串联连接提供机械强度并且在它们之间提供导电耦合。 串行接口包括一个连接器，其中形成有第一通气孔，其中构造成将第一单电池的阳极外壁和第二单元电池的阴极端子彼此导电耦合; 以及间隔件，其具有形成在其中的第二通气孔，并且被配置为设置在第二单元电池的连接器间和阳极外壁之间，以防止由于连接器的移动而引起的短路。

    Semiconductor devices having buried bit lines and methods of manufacturing semiconductor devices having buried bit lines
    14.
    发明申请
    Semiconductor devices having buried bit lines and methods of manufacturing semiconductor devices having buried bit lines 失效
    具有掩埋位线的半导体器件和具有掩埋位线的半导体器件的制造方法

    公开(公告)号：US20060131613A1

    公开(公告)日：2006-06-22

    申请号：US11240544

    申请日：2005-09-30

    Applicant: Tae-yong Kim ,  Choong-ho Lee ,  Chul Lee ,  Eun-suk Cho ,  Suk-kang Sung ,  Hye-jin Cho

    Inventor： Tae-yong Kim ,  Choong-ho Lee ,  Chul Lee ,  Eun-suk Cho ,  Suk-kang Sung ,  Hye-jin Cho

    IPC: H01L27/10

    CPC classification number: H01L27/115 ,  H01L27/11568

    Abstract: A semiconductor device includes a semiconductor substrate having a first conductivity type and having an upper portion, a pair of bit lines extending in a first direction and doped with an impurity of a second conductivity type opposite to the first conductivity type and spaced from one another in the upper portion of the semiconductor substrate, a first line formed between the pair of bit lines having a plurality of alternating recessed device isolation regions and channel regions, with each of the channel regions contacting each bit line of the at least one pair of bit lines, and word lines formed at right angles to the first lines and covering the channel regions.

    Abstract translation: 半导体器件包括具有第一导电类型并具有上部的半导体衬底，一对位线沿着第一方向延伸并且掺杂有与第一导电类型相反并且彼此间隔开的第二导电类型的杂质 所述半导体衬底的上部，形成在所述一对位线之间的第一线，所述第一线具有多个交替的凹陷器件隔离区域和沟道区域，其中每个沟道区域与所述至少一对位线的每个位线接触 以及与第一线成直角形成并覆盖沟道区的字线。

Patent Agency Ranking