公开(公告)号：US20160233221A1

公开(公告)日：2016-08-11

申请号：US15132955

申请日：2016-04-19

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Jen-Yuan CHANG ,  Chia-Ping LAI

IPC: H01L27/115 ,  H01L29/423 ,  H01L29/49 ,  H01L29/792

CPC classification number: H01L27/1157 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/11565 ,  H01L27/11568 ,  H01L29/4234 ,  H01L29/42344 ,  H01L29/4916 ,  H01L29/66833 ,  H01L29/792

Abstract: The present disclosure provides a method of fabricating a flash memory semiconductor device. In one embodiment, a method of fabricating a resistive memory array includes providing a semiconductor substrate having at least one memory cell array region and at least one shunt region, forming a control gate electrode on the memory cell array region and the shunt region, depositing a dielectric film lamination and a conductive film to cover the control gate electrode and the semiconductor substrate, forming two recesses respectively corresponding to two sides of the control gate electrode on the shunt region, patterning the conductive film to form two sidewall memory gate electrodes and one top memory gate electrode, removing one of the sidewall memory gate electrodes on the memory cell array region, and removing the dielectric film lamination which is exposed from the memory gate electrodes.

Abstract translation: 本公开提供一种制造闪速存储器半导体器件的方法。 在一个实施例中，制造电阻式存储器阵列的方法包括提供具有至少一个存储单元阵列区域和至少一个分流区域的半导体衬底，在存储单元阵列区域和分流区域上形成控制栅电极， 电介质膜层叠和导电膜覆盖控制栅电极和半导体衬底，分别对应于分流区上的控制栅电极的两侧形成两个凹槽，图案化导电膜以形成两个侧壁存储栅电极和一顶 存储器栅电极，去除存储单元阵列区域上的侧壁存储栅电极之一，以及去除从存储栅电极露出的电介质膜层叠体。