公开(公告)号：US20240099008A1

公开(公告)日：2024-03-21

申请号：US17945703

申请日：2022-09-15

Applicant: Yangtze Memory Technologies Co., Ltd.

Inventor： Tingting GAO ,  ZhiLiang XIA ,  Xiaoxin LIU ,  Xiaolong DU ,  Changzhi SUN ,  Jiayi LIU ,  ZongLiang HUO

IPC: H01L27/1157 ,  H01L27/11582

CPC classification number: H01L27/1157 ,  H01L27/11582

Abstract: According to an aspect of the disclosure, a semiconductor device is provided. The semiconductor device includes a stack structure that includes alternating insulating layers and word line layers. The semiconductor device also includes a first channel structure extending through the stack structure, a first top select gate (TSG) layer over the stack structure, and a second TSG layer over the first TSG layer. The semiconductor device further includes a second channel structure extending through the first and second TSG layers, where the second channel structure is positioned over and coupled to the first channel structure.

公开(公告)号：US20240071497A1

公开(公告)日：2024-02-29

申请号：US17898827

申请日：2022-08-30

Applicant: Micron Technology, Inc.

Inventor： Anna Maria Conti ,  Umberto Maria Meotto ,  Domenico Tuzi

IPC: G11C16/04 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11582

CPC classification number: G11C16/0483 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11582

Abstract: A variety of applications can include apparatus having memory devices, where at least one of the memory devices is a three-dimensional memory device having levels of pillars to support pillars of memory cells and one or more drain-end select gate (SGD) transistors of the memory array of the memory device. The levels of pillars are structured as a progression of pillars, where each pillar of one level is structured on and extending vertically from a different pillar of a level on which the one level is located. SGD select lines for coupling to the one or more SGD transistors are structured in a SGD stadium, where the SGD stadium is located within at least a portion of the progression of pillars.

公开(公告)号：US20240057332A1

公开(公告)日：2024-02-15

申请号：US17819097

申请日：2022-08-11

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Koichi MATSUNO

IPC: H01L27/11582 ,  H01L27/11519 ,  H01L23/522 ,  H01L23/528 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11565

CPC classification number: H01L27/11582 ,  H01L27/11519 ,  H01L23/5226 ,  H01L23/5283 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11565

Abstract: A three-dimensional memory device includes layer stacks each of which includes a first-tier alternating stack of first insulating layers and first electrically conductive layers and a second-tier alternating stack of second insulating layers and second electrically conductive layers separated by a backside trench. Memory opening fill structures vertically extend through a respective layer stack, and includes a respective vertical stack of memory elements and a respective vertical semiconductor channel. In one embodiment, a bridge structure spans an entire width of the backside trench such that a top surface of the bridge structure is located below a top surface of the second-tier alternating stack, and a bottom surface of the bridge structure is located above a bottom surface of the first-tier alternating stack. In another embodiment, a perforated bridge structure includes a plurality of vertically-extending openings.

公开(公告)号：US20240057331A1

公开(公告)日：2024-02-15

申请号：US17819081

申请日：2022-08-11

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Koichi MATSUNO

IPC: H01L27/11582 ,  H01L27/11519 ,  H01L23/522 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157

CPC classification number: H01L27/11582 ,  H01L27/11519 ,  H01L23/5226 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157

Abstract: A three-dimensional memory device includes layer stacks each of which includes a first-tier alternating stack of first insulating layers and first electrically conductive layers and a second-tier alternating stack of second insulating layers and second electrically conductive layers separated by a backside trench. Memory opening fill structures vertically extend through a respective layer stack, and includes a respective vertical stack of memory elements and a respective vertical semiconductor channel. In one embodiment, a bridge structure spans an entire width of the backside trench such that a top surface of the bridge structure is located below a top surface of the second-tier alternating stack, and a bottom surface of the bridge structure is located above a bottom surface of the first-tier alternating stack. In another embodiment, a perforated bridge structure includes a plurality of vertically-extending openings.

公开(公告)号：US20240015961A1

公开(公告)日：2024-01-11

申请号：US17861571

申请日：2022-07-11

Applicant: Yangtze Memory Technologies Co., Ltd.

Inventor： Kun ZHANG ,  Wenxi ZHOU ,  Zhiliang XIA ,  Zongliang HUO

IPC: H01L27/11556 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11582

CPC classification number: H01L27/11556 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11582

Abstract: A method for forming a three-dimensional memory device can include forming a staircase structure. An alternating layer stack is disposed and etched to form steps. A continuous layer disposed on the staircase structure continuously extends over the steps. An insulating layer is disposed on the continuous layer and a slit is formed extending through the staircase structure. The slit exposes sidewalls of the continuous layer and the steps. The sacrificial layer is removed and a cavity is formed in place of the continuous layer. An etch stop layer is disposed in the cavity and continuously extends over the steps. Openings are formed through the insulating layer and expose a portion of a lateral surface of the etch stop layer. The openings are extended through the etch stop layer to expose a lateral surface of each step of the steps. Contacts are formed in the openings.

公开(公告)号：US20230403850A1

公开(公告)日：2023-12-14

申请号：US17806406

申请日：2022-06-10

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Fumitaka AMANO ,  Ryo KAMBAYASHI

IPC: H01L27/11524 ,  H01L27/11519 ,  H01L23/48 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11565 ,  H01L27/11582

CPC classification number: H01L27/11524 ,  H01L27/11519 ,  H01L23/481 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11565 ,  H01L27/11582

Abstract: A three dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate; memory stack structures vertically extending through the alternating stack; and a backside trench fill structure. The backside trench fill structure includes a backside trench insulating spacer and a backside contact via structure. The backside contact via structure may include a tapered metallic nitride liner and at least one core fill conductive material portion. Alternatively, the backside contact via structure may include a tungsten nitride liner, a metallic nitride liner other than tungsten nitride, and at least one core fill conductive material portion.

公开(公告)号：US20230395704A1

公开(公告)日：2023-12-07

申请号：US17804997

申请日：2022-06-01

Applicant: Micron Technology, Inc.

Inventor： John Hopkins ,  Jordan D. Greenlee

IPC: H01L29/66 ,  H01L27/1157 ,  H01L29/792

CPC classification number: H01L29/66833 ,  H01L29/792 ,  H01L27/1157

Abstract: Methods, systems, and devices for self-aligned etching techniques for memory formation are described. A memory device may include a stack of alternating materials and a pillar extending through the stack of alternating materials, where the stack of alternating materials and the pillar may form a set of multiple memory cells. A polysilicon material may be formed above the pillar, where the polysilicon material may be associated with a selector device for the memory cells. A masking material may be formed above the polysilicon material and the stack of alternating materials, where the masking material may be aligned with the polysilicon material and may have a width that is greater than a width of the polysilicon material and the pillar. The masking material may prevent the polysilicon material, the pillar, and a portion of the stack of alternating materials beneath the masking material from being removed during an etching operation.

公开(公告)号：US20230352089A1

公开(公告)日：2023-11-02

申请号：US17730350

申请日：2022-04-27

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED

Inventor： Gerben Doornbos

IPC: G11C16/04 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11582 ,  H01L23/528

CPC classification number: G11C16/0483 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11582 ,  H01L23/5283

Abstract: A semiconductor device is provided. The semiconductor device includes a logic structure overlying a semiconductor substrate of the semiconductor device. The logic structure includes a plurality of logic cells. The semiconductor device includes one or more interconnection layers, overlying the logic structure, in a Back End of Line (BEOL) structure of the semiconductor device. The semiconductor device includes a non-volatile memory array, including a plurality of memory cells, overlying the logic structure and the one or more interconnection layers, wherein the non-volatile memory array at least one of overlies or is within the BEOL structure.

公开(公告)号：US20230345716A1

公开(公告)日：2023-10-26

申请号：US17660265

申请日：2022-04-22

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Tsutomu IMAI ,  Nao NAGASE ,  Chiko KUDO ,  Sadao FUKUNO

IPC: H01L27/11556 ,  H01L27/11582 ,  H01L23/528 ,  H01L23/522 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11565 ,  H01L27/1157

CPC classification number: H01L27/11556 ,  H01L27/11582 ,  H01L23/5283 ,  H01L23/5226 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11565 ,  H01L27/1157

Abstract: A sacrificial memory opening fill structure for a multi-tier memory device may include a semiconductor fill material portion a metallic fill material portion to enhance control of a vertical cross-sectional profile of an inter-tier memory opening. Multiple inter-tier dielectric layers may be employed to reduce sharp corners in a memory opening fill structure. Alternatively or additionally, a combination of an isotropic etch process followed by an anisotropic etch process may be used to form a first-tier memory opening.

公开(公告)号：US20230335193A1

公开(公告)日：2023-10-19

申请号：US17659102

申请日：2022-04-13

Applicant: Micron Technology, Inc.

Inventor： Shuangqiang Luo ,  Indra V. Chary ,  Mithun Kumar Ramasahayam

IPC: G11C16/04 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11582 ,  H01L23/528

CPC classification number: G11C16/0483 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11582 ,  H01L23/5283

Abstract: A microelectronic device comprises a stack structure comprising blocks each including a vertically alternating sequence of conductive material and insulative material arranged in tiers, at least one of the blocks comprising: a memory array region having vertically extending strings of memory cells within a horizontal area thereof; and a staircase region horizontally neighboring the memory array region. The staircase structure has steps comprising horizontal ends of the tiers; and a crest sub-region horizontally interposed between the staircase structure and the memory array region. A masking structure overlies the stack structure and has a different material composition than each of the conductive material and the insulative material. Filled slot structures are interposed between the blocks of the stack structure, at least one of the filled slot structures comprises at least one fill material that has an uppermost boundary vertically underlying an uppermost boundary of the masking structure.