公开(公告)号：US20240215251A1

公开(公告)日：2024-06-27

申请号：US18602040

申请日：2024-03-12

申请人： UNITED MICROELECTRONICS CORP.

发明人： Chia-Ching Hsu

IPC分类号： H10B43/35 ,  H01L21/28 ,  H01L29/423 ,  H01L29/66 ,  H01L29/792

CPC分类号： H10B43/35 ,  H01L29/40117 ,  H01L29/42344 ,  H01L29/66833 ,  H01L29/792

摘要： A silicon-oxide-nitride-oxide-silicon (SONOS) memory cell includes a memory gate disposed on a substrate, a dielectric layer and two charge trapping layers, wherein the dielectric layer is disposed between the substrate and the memory gate, and the two charge trapping layers are disposed at two opposite sides of the memory gate, wherein each of the charge trapping layers comprises an L-shape cross-sectional profile, and two selective gates disposed on the substrate, thereby constituting a two bit memory cell, wherein a top surface of each selective gate is higher than a top surface of the memory gate.

公开(公告)号：US20240213339A1

公开(公告)日：2024-06-27

申请号：US18598073

申请日：2024-03-07

申请人： KIOXIA CORPORATION

发明人： Tomonori KAJINO ,  Taichi IWASAKI ,  Tatsuya FUJISHIMA ,  Masayuki SHISHIDO ,  Nozomi KIDO

IPC分类号： H01L29/417 ,  G11C16/04 ,  H01L29/06 ,  H01L29/423 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

CPC分类号： H01L29/41775 ,  G11C16/0483 ,  H01L29/42328 ,  H01L29/42344 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H01L29/0607

摘要： A semiconductor memory device according to an embodiment includes a substrate, a source line, word lines, a pillar, and a first member. The first member is provided to penetrate the source line. The first member includes a first portion which is far from the substrate, and a second portion which is near the substrate. The first member includes a first contact and a first insulating film. The first contact is provided to extend from the first portion to the second portion. The first contact is electrically connected to the substrate. The first insulating film insulates the source line from the first contact. The first member includes a stepped portion at a boundary part between the first portion and the second portion.

公开(公告)号：US12021126B2

公开(公告)日：2024-06-25

申请号：US17132802

申请日：2020-12-23

申请人： Yangtze Memory Technologies Co., Ltd.

发明人： Hang Yin ,  Zhipeng Wu ,  Kai Han ,  Lu Zhang ,  Pan Wang ,  Xiangning Wang ,  Hui Zhang ,  Jingjing Geng ,  Meng Xiao

IPC分类号： H01L29/423 ,  H01L21/28 ,  H01L29/66 ,  H01L29/788 ,  H01L29/792 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

CPC分类号： H01L29/42352 ,  H01L29/40114 ,  H01L29/40117 ,  H01L29/42328 ,  H01L29/42336 ,  H01L29/42344 ,  H01L29/66545 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7889 ,  H01L29/7926 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

摘要： Aspects of the disclosure provide a method for fabricating a semiconductor device having an first stack of alternating insulating layers and sacrificial word line layers arranged over a substrate, the first stack including a core region and a staircase region. The method can include forming a first dielectric trench in the core region of the first stack, forming a second dielectric trench that is adjacent to and connected with the first dielectric trench in the staircase region of the first stack, and forming dummy channel structures extending through the first stack where the dummy channel structures are spaced apart from the second dielectric trench.

公开(公告)号：US20240206183A1

公开(公告)日：2024-06-20

申请号：US18591313

申请日：2024-02-29

申请人： Cypress Semiconductor Corporation

发明人： Chun CHEN ,  James PAK ,  Unsoon KIM ,  Inkuk KANG ,  Sung-Taeg KANG ,  Kuo Tung CHANG

IPC分类号： H10B43/40 ,  H01L21/265 ,  H01L21/28 ,  H01L21/285 ,  H01L29/423 ,  H01L29/45 ,  H01L29/49 ,  H01L29/51 ,  H01L29/66 ,  H01L29/78 ,  H01L29/792 ,  H10B41/30 ,  H10B41/49 ,  H10B43/30 ,  H10B43/35

CPC分类号： H10B43/40 ,  H01L21/26513 ,  H01L21/28052 ,  H01L21/28518 ,  H01L29/40114 ,  H01L29/40117 ,  H01L29/42328 ,  H01L29/42344 ,  H01L29/456 ,  H01L29/4933 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/66833 ,  H01L29/7833 ,  H01L29/792 ,  H10B41/30 ,  H10B41/49 ,  H10B43/30 ,  H10B43/35 ,  H01L29/517

摘要： A semiconductor device and methods of fabrication the same are disclosed. In one embodiment, the semiconductor device may include a non-volatile memory (NVM) cell including a memory gate stack and a select gate stack separated by an inter-gate dielectric disposed in a memory region of a substrate, a low voltage field-effect transistor (LVFET) including a first high-K metal-gate (HKMG) stack disposed in a peripheral region of the substrate, and a high voltage field-effect transistor (HVFET) including a second HKMG stack disposed in the peripheral region, in which top surfaces of the memory gate stack and the select gate stack of the NVM cell, the LVFET, and the HVFET have an approximately same elevation from the substrate or are substantially co-planar. Other embodiments are also disclosed within.

公开(公告)号：US20240170551A1

公开(公告)日：2024-05-23

申请号：US18430522

申请日：2024-02-01

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Meng-Han LIN ,  Wei-Cheng WU ,  Te-Hsin CHIU

IPC分类号： H01L29/423 ,  H01L21/02 ,  H01L21/28 ,  H01L29/66 ,  H01L29/792 ,  H10B43/35 ,  H10B43/40

CPC分类号： H01L29/42368 ,  H01L21/02244 ,  H01L29/40117 ,  H01L29/42344 ,  H01L29/66833 ,  H01L29/792 ,  H10B43/35 ,  H10B43/40

摘要： A semiconductor device includes a semiconductor substrate, a control gate, a select gate, a charge trapping structure, a dielectric structure, and a spacer. The control gate and the select gate are over a channel region of the semiconductor substrate and separated from each other. The charge trapping structure is between the control gate and the semiconductor substrate. The dielectric structure is between the select gate and the semiconductor substrate. The dielectric structure has a first part and a second part, the first part is between the charge trapping structure and the second part, and the second part is thicker than the first part. The select gate is between the spacer and the control gate, and the select gate is separated from the spacer by the second part of the dielectric structure.

公开(公告)号：US11967623B2

公开(公告)日：2024-04-23

申请号：US17388233

申请日：2021-07-29

申请人： Samsung Electronics Co., Ltd.

发明人： Sunggil Kim ,  Jung-Hwan Kim ,  Gukhyon Yon

IPC分类号： H01L29/423 ,  H01L23/00 ,  H01L23/48 ,  H01L23/498 ,  H01L23/538 ,  H01L25/065 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/40 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40

CPC分类号： H01L29/42344 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49833 ,  H01L23/49838 ,  H01L23/5385 ,  H01L23/5386 ,  H01L24/08 ,  H01L24/32 ,  H01L25/0652 ,  H01L25/0657 ,  H01L29/42328 ,  H01L2224/08146 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2225/0651 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2225/06562 ,  H01L2924/1431 ,  H01L2924/1436 ,  H01L2924/1438 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/40 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40

摘要： Disclosed is a semiconductor device comprising gate stack structures on a substrate, separation structures extending in a first direction on the substrate and separating the gate stack structures, and vertical structures penetrating the gate stack structures. Each gate stack structure includes cell dielectric layers and electrodes including upper electrodes, a barrier layer extending between the electrodes and the cell dielectric layers, a separation dielectric pattern extending in the first direction and penetrating the upper electrodes to separate each upper electrode into pieces that are spaced apart from each other in a second direction intersecting the first direction, and capping patterns between the separation dielectric pattern and the upper electrodes. The capping patterns are on sidewalls of each upper electrode and spaced apart from each other in a third direction perpendicular to a top surface of the substrate. Each capping pattern is on a sidewall of the barrier layer.

公开(公告)号：US11948639B2

公开(公告)日：2024-04-02

申请号：US17368395

申请日：2021-07-06

申请人： Micron Technology, Inc.

发明人： John D. Hopkins ,  Alyssa N. Scarbrough

IPC分类号： H10B41/27 ,  G11C16/04 ,  H01L21/28 ,  H01L29/423 ,  H10B41/10 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

CPC分类号： G11C16/0483 ,  H01L29/40114 ,  H01L29/40117 ,  H01L29/42328 ,  H01L29/42344 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

摘要： A method used in forming a memory array comprising strings of memory cells comprises forming a stack comprising vertically-alternating first tiers and second tiers comprising laterally-spaced memory-block regions having horizontally-elongated trenches there-between. Two of the first tiers have different vertical thicknesses relative one another. Channel-material strings of memory cells extend through the first tiers and the second tiers. Through the horizontally-elongated trenches, first conductive material is formed in void space in the two first tiers. The first conductive material fills the first tier of the two first tiers that has a smaller of the different vertical thicknesses in individual of the memory-block regions. The first conductive material less-than-fills the first tier of the two first tiers that has a larger of the different vertical thicknesses in the individual memory-block regions. Through the horizontally-elongated trenches, the first conductive material is isotropically etched from the first tier having the larger vertical thickness in the individual memory-block regions to leave the first conductive material in the first tier having the smaller vertical thickness in the individual memory-block regions. After the isotropically etching of the first conductive material and through the horizontally-elongated trenches, second conductive material is formed in the first tier having the larger vertical thickness in the individual memory-block regions. Other embodiments, including structure independent of method, are disclosed.

公开(公告)号：US11910607B2

公开(公告)日：2024-02-20

申请号：US17881707

申请日：2022-08-05

申请人： Samsung Electronics Co., Ltd.

发明人： Jung-Hwan Kim ,  Sunggil Kim ,  Dongkyum Kim ,  Seulye Kim ,  Ji-Hoon Choi

IPC分类号： H01L21/00 ,  H10B43/27 ,  H01L29/04 ,  H01L29/792 ,  H01L29/423 ,  H10B43/10 ,  H10B43/35 ,  H10B43/40

CPC分类号： H10B43/27 ,  H01L29/04 ,  H01L29/42344 ,  H01L29/7926 ,  H10B43/10 ,  H10B43/35 ,  H10B43/40

摘要： A three-dimensional semiconductor memory device is disclosed. The device may include a first source conductive pattern comprising a polycrystalline material including first crystal grains on a substrate, the substrate may comprising a polycrystalline material including second crystal grains, a grain size of the first crystal grains being smaller than a grain size of the second crystal grains, a stack including a plurality of gate electrodes, the plurality of gates stacked on the first source conductive pattern, and a vertical channel portion penetrating the stack and the first source conductive pattern, and the vertical channel portion being in contact with a side surface of the first source conductive pattern.

公开(公告)号：US11888041B2

公开(公告)日：2024-01-30

申请号：US17825542

申请日：2022-05-26

申请人： Kioxia Corporation

发明人： Megumi Ishiduki ,  Hiroshi Nakaki ,  Takamasa Ito

IPC分类号： H01L29/423 ,  H01L29/66 ,  H01L29/792 ,  H10B43/10 ,  H10B43/27 ,  H10B43/50 ,  H01L23/528 ,  H01L21/768 ,  H10B41/20 ,  H10B43/35 ,  H10B43/40 ,  H10B43/30 ,  H01L27/10

CPC分类号： H01L29/42344 ,  H01L29/66833 ,  H01L29/7926 ,  H10B43/10 ,  H10B43/27 ,  H10B43/50 ,  H01L21/76895 ,  H01L23/528 ,  H01L27/10 ,  H10B41/20 ,  H10B43/30 ,  H10B43/35 ,  H10B43/40

摘要： A semiconductor device includes a base body, a stacked body on the base body and a first columnar part. The base body includes a substrate, a first insulating film on the substrate, a first conductive film on the first insulating film, and a first semiconductor part on the first conductive film. The stacked body includes conductive layers and insulating layers stacked alternately in a stacking direction. The first columnar part is provided inside the stacked body and the first semiconductor part. The first columnar part includes a semiconductor body and a memory film between the semiconductor body and conductive layers. The semiconductor body extends in the stacking direction. The first columnar part has a first diameter and a second diameter in a first direction crossing the stacking direction. The first diameter inside the first semiconductor part is larger than the second diameter inside the stacked body.

公开(公告)号：US20240008277A1

公开(公告)日：2024-01-04

申请号：US18469666

申请日：2023-09-19

申请人： KIOXIA CORPORATION

发明人： Takanobu ONO ,  Yusuke DOHMAE

IPC分类号： H10B43/27 ,  H01L21/822 ,  H01L29/423 ,  H01L21/28 ,  H10B43/35

CPC分类号： H10B43/27 ,  H01L21/822 ,  H01L29/42344 ,  H01L29/40117 ,  H10B43/35

摘要： A semiconductor wafer according to the present embodiment includes a plurality of semiconductor chip regions and a division region. The plurality of semiconductor chip regions have a semiconductor element. The division region is provided between the semiconductor chip regions adjacent to each other. A first stacked body is provided on the division region. The first stacked body is configured with a plurality of first material films and a plurality of second material films alternately stacked.