公开(公告)号：US12243805B2

公开(公告)日：2025-03-04

申请号：US17815997

申请日：2022-07-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jian-Hong Lin ,  Hsin-Chun Chang ,  Ming-Hong Hsieh ,  Ming-Yih Wang ,  Yinlung Lu

IPC: H01L23/48 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528

Abstract: An integrated circuit (IC) with through-circuit vias (TCVs) and methods of forming the same are disclosed. The IC includes a semiconductor device, first and second interconnect structures disposed on first and second surfaces of the semiconductor device, respectively, first and second inter-layer dielectric (ILD) layers disposed on front and back surfaces of the substrate, respectively, and a TCV disposed within the first and second interconnect structures, the first and second ILD layers, and the substrate. The TCV is spaced apart from the semiconductor device by a portion of the substrate and portions of the first and second ILD layers. A first end of the TCV, disposed over the front surface of the substrate, is connected to a conductive line of the first interconnect structure and a second end of the TCV, disposed over the back surface of the substrate, is connected to a conductive line of the second interconnect structure.

公开(公告)号：US11955441B2

公开(公告)日：2024-04-09

申请号：US17706039

申请日：2022-03-28

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Jian-Hong Lin ,  Kuo-Yen Liu ,  Hsin-Chun Chang ,  Tzu-Li Lee ,  Yu-Ching Lee ,  Yih-Ching Wang

IPC: H01L23/00 ,  H01L23/522 ,  H01L23/58 ,  H01L27/02 ,  H01L21/768

CPC classification number: H01L23/562 ,  H01L23/522 ,  H01L23/5226 ,  H01L23/585 ,  H01L27/0248 ,  H01L21/76805 ,  H01L2224/06519 ,  H01L2224/09519 ,  H01L2224/30519 ,  H01L2224/33519

Abstract: An interconnect structure comprises a first dielectric layer, a first metal layer, a second dielectric layer, a metal via, and a second metal layer. The first dielectric layer is over a substrate. The first metal layer is over the first dielectric layer. The first metal layer comprises a first portion and a second portion spaced apart from the first portion. The second dielectric layer is over the first metal layer. The metal via has an upper portion in the second dielectric layer, a middle portion between the first and second portions of the first metal layer, and a lower portion in the first dielectric layer. The second metal layer is over the metal via. From a top view the second metal layer comprises a metal line having longitudinal sides respectively set back from opposite sides of the first portion of the first metal layer.

公开(公告)号：US20220367323A1

公开(公告)日：2022-11-17

申请号：US17815997

申请日：2022-07-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jian-Hong Lin ,  Hsin-Chun Chang ,  Ming-Hong Hsieh ,  Ming-Yih Wang ,  Yinlung Lu

IPC: H01L23/48 ,  H01L23/522 ,  H01L21/768 ,  H01L23/528

Abstract: An integrated circuit (IC) with through-circuit vias (TCVs) and methods of forming the same are disclosed. The IC includes a semiconductor device, first and second interconnect structures disposed on first and second surfaces of the semiconductor device, respectively, first and second inter-layer dielectric (ILD) layers disposed on front and back surfaces of the substrate, respectively, and a TCV disposed within the first and second interconnect structures, the first and second ILD layers, and the substrate. The TCV is spaced apart from the semiconductor device by a portion of the substrate and portions of the first and second ILD layers. A first end of the TCV, disposed over the front surface of the substrate, is connected to a conductive line of the first interconnect structure and a second end of the TCV, disposed over the back surface of the substrate, is connected to a conductive line of the second interconnect structure.

公开(公告)号：US11302654B2

公开(公告)日：2022-04-12

申请号：US17018381

申请日：2020-09-11

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Jian-Hong Lin ,  Kuo-Yen Liu ,  Hsin-Chun Chang ,  Tzu-Li Lee ,  Yu-Ching Lee ,  Yih-Ching Wang

IPC: H01L21/768 ,  H01L23/00 ,  H01L23/58 ,  H01L27/02 ,  H01L23/522

Abstract: A method includes depositing a first dielectric layer over a substrate; forming a first dummy metal layer over the first dielectric layer, wherein the first dummy metal layer has first and second portions laterally separated from each other; depositing a second dielectric layer over the first dummy metal layer; etching an opening having an upper portion in the second dielectric layer, a middle portion between the first and second portions of the first dummy metal layer, and a lower portion in the first dielectric layer, wherein a width of the lower portion of the opening is greater than a width of the middle portion of the opening, and a bottom of the opening is higher than a bottom of the first dielectric layer; and forming a dummy via in the opening and a second dummy metal layer over the dummy via and the second dielectric layer.

公开(公告)号：US09356016B2

公开(公告)日：2016-05-31

申请号：US14516673

申请日：2014-10-17

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chin-Shan Wang ,  Jian-Hong Lin ,  Shun-Yi Lee

IPC: H01L27/07 ,  H01L27/06 ,  H01L29/49 ,  H01L49/02 ,  H01L29/423 ,  H01L29/66

CPC classification number: H01L21/76895 ,  H01L21/76831 ,  H01L23/485 ,  H01L23/5223 ,  H01L27/0629 ,  H01L27/0635 ,  H01L27/0716 ,  H01L28/60 ,  H01L28/86 ,  H01L28/90 ,  H01L29/42372 ,  H01L29/4916 ,  H01L29/66568 ,  H01L29/6659 ,  H01L29/94 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device includes a semiconductor substrate, a transistor, a conductive contact and a capacitor. The transistor is formed on the semiconductor substrate, and the transistor includes a gate, a source and a drain. The conductive contact is formed on and in contact with at least one of the source and the drain. The capacitor includes a first electrode and a second electrode spaced apart from first electrode. At least one of the first and second electrodes extends on substantially the same level as the conductive contact or the gate. A method of forming the semiconductor device is provided as well.

Abstract translation: 半导体器件包括半导体衬底，晶体管，导电接触和电容器。 晶体管形成在半导体衬底上，晶体管包括栅极，源极和漏极。 导电接触形成在源极和漏极中的至少一个上并与其接触。 电容器包括第一电极和与第一电极间隔开的第二电极。 第一和第二电极中的至少一个在与导电接触件或栅极基本上相同的水平上延伸。 还提供了形成半导体器件的方法。