公开(公告)号：US08365126B2

公开(公告)日：2013-01-29

申请号：US12630619

申请日：2009-12-03

申请人： Takashi Gotou

发明人： Takashi Gotou

IPC分类号： G06F17/50 ,  G06F9/455

CPC分类号： G06F17/5068

摘要： An integrated circuit design apparatus includes a macro signal terminal position determination unit that determines temporary arrangement positions of a scan-in terminal and a scan-out terminal of each of a number of macros. The unit updates layout information of an integrated circuit based on the temporary arrangement positions. The apparatus includes an initial scan path route determination unit that updates scan path connection information, such that one of the macros arranged in a closest distance is connected in turn starting with a scan-in external terminal, with reference to the updated layout information and the scan path connection information. The apparatus include a scan path re-routing unit that determines a scan path connection order, such that a scan path total wiring length becomes shortest, with reference to the updated layout information and the updated scan path connection information. This unit updates the scan path connection information based on this determined order.

摘要翻译： 集成电路设计装置包括宏信号终端位置确定单元，其确定多个宏中的每一个的扫描终端和扫描输出终端的临时布置位置。 该单元基于临时布置位置来更新集成电路的布局信息。 该装置包括：初始扫描路径路由确定单元，其更新扫描路径连接信息，使得参考更新的布局信息，以最接近距离布置的宏中的一个依次从扫描外部终端开始连接 扫描路径连接信息。 该装置包括参考更新的布局信息和更新的扫描路径连接信息来确定扫描路径连接顺序的扫描路径重路由单元，使得扫描路径总布线长度变得最短。 本机根据此确定的顺序更新扫描路径连接信息。

公开(公告)号：US08225263B2

公开(公告)日：2012-07-17

申请号：US12408218

申请日：2009-03-20

申请人： Takashi Gotou

发明人： Takashi Gotou

IPC分类号： G06F17/50 ,  G06F9/455 ,  G06F11/22

CPC分类号： G06F17/5081 ,  G06F17/5077

摘要： A design method of a semiconductor integrated circuit carried out by a computer, including: a DRC step of performing a design rule check (Design Rule Check) with reference to layout information on an internal wiring in a capacitor cell and layout information on a signal wiring in the semiconductor integrated circuit; an integration step of integrating layout information on the internal wiring into layout information on the signal wiring when being determined in the DRC step that there is an error; and an elimination step of eliminating an error portion in the internal wiring from the integrated layout information.

摘要翻译： 一种由计算机执行的半导体集成电路的设计方法，包括：参考电容器单元的内部布线的布局信息和信号布线的布局信息执行设计规则检查（设计规则检查）的DRC步骤 在半导体集成电路中; 在DRC步骤中确定存在错误的情况下，将内部布线信息集成到信号布线布局信息的集成步骤; 以及从集成布局信息中消除内部布线中的错误部分的消除步骤。

公开(公告)号：US08117583B2

公开(公告)日：2012-02-14

申请号：US12036643

申请日：2008-02-25

申请人： Takashi Gotou

发明人： Takashi Gotou

IPC分类号： G06F17/50

CPC分类号： G06F17/5068

摘要： Provided is an integrated circuit layout design supporting device which can reduce the wiring length by avoiding bypass wirings when a plurality of same-type macro blocks are used. The integrated circuit layout design supporting device includes a terminal coordinate calculation control unit and a layout processing control unit. The terminal coordinate calculation control unit considers the plurality of same-type macro blocks included in a plurality of types of macro blocks as each of different types of macro blocks, and calculates the optimum coordinate positions of each macro terminal of each macro block. The layout processing control unit performs various types of wiring layout processing related to each of the macro terminals based on each of the macro terminal positions calculated by the terminal coordinate calculation control unit.

摘要翻译： 提供了一种集成电路布局设计支持装置，当使用多个相同类型的宏块时，可以通过避免旁路布线来减少布线长度。 集成电路布局设计支持装置包括终端坐标计算控制单元和布局处理控制单元。 终端坐标计算控制单元将包括在多个宏块中的多个相同类型宏块视为不同类型的宏块，并计算每个宏块的每个宏终端的最佳坐标位置。 布局处理控制单元基于由终端坐标计算控制单元计算的每个宏终端位置执行与每个宏终端相关的各种类型的布线布局处理。

公开(公告)号：US20120017753A1

公开(公告)日：2012-01-26

申请号：US13262448

申请日：2010-03-24

申请人： Kiyoshi Asahina ,  Kenji Koide ,  Takashi Gotou ,  Hideaki Shimoda ,  Ryusuke Kitamura ,  Nakaba Tsutsui

发明人： Kiyoshi Asahina ,  Kenji Koide ,  Takashi Gotou ,  Hideaki Shimoda ,  Ryusuke Kitamura ,  Nakaba Tsutsui

IPC分类号： F42D5/04

CPC分类号： F42B33/067 ,  C06B21/0091 ,  F23G5/50 ,  F23G7/00 ,  F23G2208/10 ,  F23G2209/16 ,  F42B33/0214 ,  F42D3/00

摘要： A blast treatment method and an apparatus, which can perform the blast treatment of a treatment subject by using and securely initiating a blasting explosive having fluidity. The blast treatment method includes: a blasting preparation operation of housing a blasting explosive having fluidity in a container and placing the blasting explosive around a treatment subject as well as attaching an initiation device to the container; a housing operation of housing the container, the blasting explosive, and the treatment subject in a chamber; a decompression operation of decompressing the inside of the chamber; and a blasting operation of initiating the blasting explosive and blasting the treatment subject with the blasting explosive. In the decompression operation, the inside of the chamber is decompressed while a gas vent portion regulates the escape of the blasting explosive to the outside of the container and permits the escape of gases in the container to the outside.

摘要翻译： 一种喷砂处理方法和装置，其可以通过使用并可靠地起始具有流动性的爆破炸药来对处理对象进行喷砂处理。 喷砂处理方法包括：在容器内容纳具有流动性的爆破炸药的爆破准备操作，将爆破炸药置于处理对象周围，以及将引发装置附着到容器上; 在容器中容纳容器，爆破炸药和处理对象的住房操作; 减压室内减压操作; 以及爆破作业，起爆爆炸物并用爆破炸药爆破处理对象。 在减压操作中，室内减压，同时排气部分调节爆破炸药逃逸到容器的外部，并允许容器内的气体逸出到外面。

公开(公告)号：US20060081881A1

公开(公告)日：2006-04-20

申请号：US11250581

申请日：2005-10-17

申请人： Takashi Gotou

发明人： Takashi Gotou

IPC分类号： H01L27/10

CPC分类号： G06F17/5077

摘要： A circuit wiring laying-out apparatus includes a wiring device that moves automatically a wiring in a first region to a second region, to make uniform a number of wirings in the circuit.

摘要翻译： 电路布线布置装置包括：自动地将第一区域中的布线移动到第二区域的布线装置，以使电路中的多个布线均匀。