公开(公告)号：US07133730B1

公开(公告)日：2006-11-07

申请号：US09594995

申请日：2000-06-14

申请人： Masaki Katayama ,  Yasuhiro Fujimura

发明人： Masaki Katayama ,  Yasuhiro Fujimura

IPC分类号： G06F17/00 ,  H04R5/02 ,  G05B19/02 ,  H04B1/20

CPC分类号： H04L49/90

摘要： Control data is stored in a first memory. Control data inputted from an external device is stored a second rewritable memory. A control section selects either one of the first and second memories and controls operation according to a control program using the control data stored in the memory selected. An image corresponding to control data is displayed on a display screen. Through the image, it is possible to select particular control data from a plurality of control data. The control data selected via the screen is sent to the second memory. Processing can be therefore executed to appropriately cope with requirements of the user.

摘要翻译： 控制数据存储在第一存储器中。 从外部设备输入的控制数据被存储在第二可重写存储器中。 控制部分选择第一和第二存储器中的一个，并且使用存储在所选择的存储器中的控制数据根据控制程序控制操作。 在显示画面上显示与控制数据对应的图像。 通过图像，可以从多个控制数据中选择特定的控制数据。 通过屏幕选择的控制数据被发送到第二存储器。 因此可以执行处理以适当地应对用户的要求。

公开(公告)号：US20080013645A1

公开(公告)日：2008-01-17

申请号：US11777181

申请日：2007-07-12

申请人： Takashi MUTO ,  Yasuhiro Fujimura ,  Keiichi Higeta ,  Junji Baba ,  Takayuki Muranaka ,  Isao Kimura

发明人： Takashi MUTO ,  Yasuhiro Fujimura ,  Keiichi Higeta ,  Junji Baba ,  Takayuki Muranaka ,  Isao Kimura

IPC分类号： H04L12/28

CPC分类号： H04L25/0274 ,  H04L25/0288

摘要： In a data transfer device which cancels an offset of a differential amplifier for amplifying a received signal and an offset caused by characteristics of a differential transmission line and selects optimum conditions such as pre-emphasis amount of an output pre-emphasis circuit, a first chip (transmission side LSI=transfer engine 210) and a second chip (reception side LSI=multiplexing engine 330) are connected to each other through differential transmission line 430 and a SerDes (serializer) 401 and a SerDes (deserializer) 402 are used to make signal transmission, so that optimum setting conditions of an offset amount of an offset cancellation circuit included in an input buffer amplifier and a pre-emphasis amount of pre-emphasis circuit included in an output buffer are decided in training using a training PRBS generator 560 and a training PRBS comparator 570.

摘要翻译： 在消除用于放大接收信号的差分放大器的偏移的数据传送装置和由差分传输线的特性引起的偏移，并且选择最佳条件，例如输出预加重电路的预加重量，第一芯片 （发送侧LSI =传送引擎210）和第二芯片（接收侧LSI =多路复用引擎330）通过差分传输线路430彼此连接，并且使用SerDes（串行器）401和SerDes（解串器）402来进行 信号传输，使得包括在输入缓冲放大器中的偏移消除电路的偏移量的最佳设置条件和包括在输出缓冲器中的预加重电路的预加重量在训练中使用训练PRBS发生器560和 训练PRBS比较器570。

公开(公告)号：US06747678B1

公开(公告)日：2004-06-08

申请号：US09594307

申请日：2000-06-15

申请人： Masaki Katayama ,  Yasuhiro Fujimura ,  Tetsuya Matsuyama

发明人： Masaki Katayama ,  Yasuhiro Fujimura ,  Tetsuya Matsuyama

IPC分类号： G06F314

CPC分类号： H04S1/007

摘要： As a desired digital signal processor (DSP) mode is selected from DSP setting buttons displayed in a DSP setting window, only those slide bars for changing parameters of the selected DSP mode are displayed. As a slider bar corresponding to a parameter to be changed is selected from the slide bars displayed in the DSP setting window, an area of an impulse response diagram to be influenced by a change in the parameter value is indicated in a discriminatory manner by an arrow or the like. A user can visually confirm the acoustic effect to be changed by the value of each DSP parameter and can change the parameter value with ease.

摘要翻译： 从DSP设置窗口中显示的DSP设置按钮中选择所需的数字信号处理器（DSP）模式时，仅显示用于更改所选DSP模式参数的滑条。 由于在DSP设定窗口中显示的幻灯片中选择与要更改的参数相对应的滑条，所以以参数值的变化影响的脉冲响应图的区域用箭头表示 或类似物。 用户可以通过每个DSP参数的值来视觉上确认要改变的声音效果，并且可以轻松地改变参数值。

公开(公告)号：US08086889B2

公开(公告)日：2011-12-27

申请号：US12256535

申请日：2008-10-23

申请人： Yuichi Ito ,  Yasuhiro Fujimura ,  Koki Tsutsumida ,  Shigeru Nakahara

发明人： Yuichi Ito ,  Yasuhiro Fujimura ,  Koki Tsutsumida ,  Shigeru Nakahara

IPC分类号： G06F1/04 ,  G01R31/28

CPC分类号： G01R31/318552

摘要： A scan chain group structure in which a group of scan chains formed for each clock tree system in an LSI is subjected to a reconnection process so that the scan chain group is not present across a plurality of clock distribution regions obtained by dividing the clock-supplied region of the clock tree of one system and that the connection distance thereof in the distribution region becomes short, a test clock input mechanism in which test clocks to be input to the distribution regions are independent sub-clock phases, and an on/off mechanism of the clocks to be input to the distribution regions are realized. Further, the scan-in/out and scan test performed at the same time are limited in one region or between single regions, and tests in all regions and between all regions are carried out by a plurality of times of test steps.

摘要翻译： 扫描链组结构，其中为LSI中的每个时钟树系统形成的一组扫描链进行重新连接处理，使得扫描链组不存在于通过对由时钟提供的 一个系统的时钟树的区域，并且分配区域中的连接距离变短;测试时钟输入机构，其中要输入到分配区域的测试时钟是独立的子时钟相位;以及开/关机构 实现要输入到分配区域的时钟。 此外，同时执行的扫描/扫描测试在一个区域或单个区域之间被限制，并且在所有区域中以及在所有区域之间的测试通过多次测试步骤来执行。

公开(公告)号：US20090113230A1

公开(公告)日：2009-04-30

申请号：US12256535

申请日：2008-10-23

申请人： Yuichi Ito ,  Yasuhiro Fujimura ,  Koki Tsutsumida ,  Shigeru Nakahara

发明人： Yuichi Ito ,  Yasuhiro Fujimura ,  Koki Tsutsumida ,  Shigeru Nakahara

IPC分类号： G01R31/3183 ,  G06F11/263 ,  G06F1/10 ,  H01L21/8232

CPC分类号： G01R31/318552

摘要： A scan chain group structure in which a group of scan chains formed for each clock tree system in an LSI is subjected to a reconnection process so that the scan chain group is not present across a plurality of clock distribution regions obtained by dividing the clock-supplied region of the clock tree of one system and that the connection distance thereof in the distribution region becomes short, a test clock input mechanism in which test clocks to be input to the distribution regions are independent sub-clock phases, and an on/off mechanism of the clocks to be input to the distribution regions are realized. Further, the scan-in/out and scan test performed at the same time are limited in one region or between single regions, and tests in all regions and between all regions are carried out by a plurality of times of test steps.

摘要翻译： 扫描链组结构，其中为LSI中的每个时钟树系统形成的一组扫描链进行重新连接处理，使得扫描链组不存在于通过对由时钟提供的 一个系统的时钟树的区域，并且分配区域中的连接距离变短;测试时钟输入机构，其中要输入到分配区域的测试时钟是独立的子时钟相位;以及开/关机构 实现要输入到分配区域的时钟。 此外，同时执行的扫描/扫描测试在一个区域或单个区域之间被限制，并且通过多次测试步骤在所有区域和所有区域之间进行测试。

公开(公告)号：US07260057B2

公开(公告)日：2007-08-21

申请号：US10336723

申请日：2003-01-06

申请人： Shunsuke Toyoshima ,  Yasuhiro Fujimura ,  Toshiro Takahashi

发明人： Shunsuke Toyoshima ,  Yasuhiro Fujimura ,  Toshiro Takahashi

IPC分类号： H04L5/04

CPC分类号： H04L25/061

摘要： The invention provides a technique that enables a correct discrimination of reception data, when the supply voltage of a semiconductor integrated circuit having a simultaneous bi-directional interface is decreased. The data transmission system is provided with input circuits constituting a simultaneous bi-directional interface by the number of reference voltages used. Each of the input circuits is supplied with a fixed reference voltage, the input circuit supplied with a higher reference voltage employs a differential amplifier with n-channel MOSFETs served as input differential devices, and the input circuit supplied with a lower reference voltage employs a differential amplifier with p-channel MOSFETs served as input differential devices, in which selectors switch the outputs of the two differential amplifiers in correspondence with the output data of their own. Thus, the system attains the reception data.

摘要翻译： 当具有同时双向接口的半导体集成电路的电源电压降低时，本发明提供了能够对接收数据进行正确鉴别的技术。 数据传输系统具有通过所使用的参考电压数量构成同时双向接口的输入电路。 为每个输入电路提供固定的参考电压，提供较高参考电压的输入电路采用差分放大器，其中n沟道MOSFET用作输入差分器件，而提供较低参考电压的输入电路采用差分 具有p沟道MOSFET的放大器用作输入差分器件，其中选择器根据其自身的输出数据切换两个差分放大器的输出。 因此，系统获得接收数据。

公开(公告)号：US07050869B1

公开(公告)日：2006-05-23

申请号：US09593866

申请日：2000-06-14

申请人： Masaki Katayama ,  Yasuhiro Fujimura ,  Tetsuya Matsuyama

发明人： Masaki Katayama ,  Yasuhiro Fujimura ,  Tetsuya Matsuyama

IPC分类号： G06F17/00

CPC分类号： G11B27/028 ,  G11B27/031

摘要： To change a value of a DSP parameter in a DSP setting screen, a user selects from parameter operators a parameter value to be changed. In an image picture displayed on the DSP setting screen, a size, a color, and the like corresponding to substance of the pertinent parameter are changed according to the value of the parameter. The user can visually perceive effect of the value of each DSP parameter on an acoustic effect and can easily change the value of each DSP parameter.

摘要翻译： 要在DSP设置屏幕中更改DSP参数的值，用户从参数运算符中选择要更改的参数值。 在DSP设定画面上显示的图像画面中，根据该参数的值来改变与有关参数的实质对应的大小，颜色等。 用户可以在视觉上感知每个DSP参数的值对声学效应的影响，并且可以容易地改变每个DSP参数的值。

公开(公告)号：US5351211A

公开(公告)日：1994-09-27

申请号：US95204

申请日：1993-07-23

申请人： Keiichi Higeta ,  Sohei Omori ,  Yasuhiro Fujimura ,  Etsuko Iwamoto ,  Akihisa Uchida

发明人： Keiichi Higeta ,  Sohei Omori ,  Yasuhiro Fujimura ,  Etsuko Iwamoto ,  Akihisa Uchida

IPC分类号： G01R31/28 ,  G01R31/30 ,  G11C7/22 ,  H01L21/66 ,  G11C7/00 ,  G11C29/00

CPC分类号： G01R31/3016 ,  G11C7/22

摘要： An integrated circuit including latch circuits disposed on the input and output sides of an object circuit the delay time of which is to be measured, respectively, and a variable delay circuit capable of arbitrarily delaying a timing signal supplied from outside or a timing signal generated inside the integrated circuit by an instruction from outside. The timing signal and a delay signal obtained by delaying the input signal by the variable delay circuit are supplied as clock signals to the latch circuits, and the signal passing through the variable delay circuit is fed back to the input side so as to constitute an oscillation circuit, the oscillation signal of which can be outputted to outside. A signal delayed by a desired time can be automatically generated inside the semiconductor integrated circuit on the basis of this timing signal.

摘要翻译： 一种集成电路，包括分别设置在对象电路的输入和输出侧的锁存电路，其延迟时间分别被测量;以及可变延迟电路，其能够任意地延迟从外部提供的定时信号或内部产生的定时信号 集成电路由外部指令组成。 通过可变延迟电路延迟输入信号而获得的定时信号和延迟信号作为时钟信号提供给锁存电路，并且通过可变延迟电路的信号被反馈到输入侧，以构成振荡 电路，其振荡信号可以输出到外部。 可以在该定时信号的基础上在半导体集成电路内自动生成延迟所需时间的信号。