公开(公告)号：US20250021242A1

公开(公告)日：2025-01-16

申请号：US18771764

申请日：2024-07-12

Applicant: Texas Instruments Incorporated

Inventor： David Foley ,  Saya Goud Langadi ,  Alexander Tessarolo ,  Venkatesh Natarajan

IPC: G06F3/06

Abstract: In described examples, an integrated circuit (IC) includes a memory and a processor coupled to the memory. The processor is configured to execute a discontinuity instruction, which specifies a memory address, to transition from executing according to a first stack pointer to executing according to a second stack pointer. The first stack pointer is copied from an active stack register to an inactive first stack pointer register. The processor determines whether the specified memory address stores a stack entry instruction that corresponds to the discontinuity instruction. If it does, the second stack pointer is copied from the inactive second stack pointer register to the active stack register, and the processor executes the stack entry instruction and begins execution according to the second stack pointer.

公开(公告)号：US20240427601A1

公开(公告)日：2024-12-26

申请号：US18441796

申请日：2024-02-14

Applicant: Texas Instruments Incorporated

Inventor： Venkatesh Natarajan ,  Alexander Tessarolo

IPC: G06F9/30 ,  G06F9/38

Abstract: Methods, apparatus, systems, and articles of manufacture are described to facilitate unaligned byte stream operations. An example apparatus includes a register including a first portion and a second portion; and a decoder to, responsive to obtaining an instruction, move at least some data from the first portion of the register to the second portion of the register based on an address identified in the instruction; an interface to cause a multiple-byte read to access data from an aligned address of memory; and the decoder to store the accessed data into the first portion of the register based on the address identified in the instruction.

公开(公告)号：US11733969B2

公开(公告)日：2023-08-22

申请号：US17378916

申请日：2021-07-19

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Prasanth Viswanathan Pillai ,  Richard Mark Poley ,  Venkatesh Natarajan ,  Alexander Tessarolo

IPC: G06F7/548

CPC classification number: G06F7/548

Abstract: In described examples, an apparatus is arranged to generate a linear term, a quadratic term, and a constant term of a transcendental function with, respectively, a first circuit, a second circuit, and a third circuit in response to least significant bits of an input operand and in response to, respectively, a first, a second, and a third table value that is retrieved in response to, respectively, a first, a second, and a third index generated in response to most significant bits of the input operand. The third circuit is further arranged to generate a mantissa of an output operand in response to a sum of the linear term, the quadratic term, and the constant term.

公开(公告)号：US11099815B2

公开(公告)日：2021-08-24

申请号：US16934539

申请日：2020-07-21

Applicant: Texas Instruments Incorporated

Inventor： Prasanth Viswanathan Pillai ,  Richard Mark Poley ,  Venkatesh Natarajan ,  Alexander Tessarolo

IPC: G06F7/548

Abstract: In described examples, an apparatus is arranged to generate a linear term, a quadratic term, and a constant term of a transcendental function with, respectively, a first circuit, a second circuit, and a third circuit in response to least significant bits of an input operand and in response to, respectively, a first, a second, and a third table value that is retrieved in response to, respectively, a first, a second, and a third index generated in response to most significant bits of the input operand. The third circuit is further arranged to generate a mantissa of an output operand in response to a sum of the linear term, the quadratic term, and the constant term.

公开(公告)号：US20190369962A1

公开(公告)日：2019-12-05

申请号：US16000736

申请日：2018-06-05

Applicant: Texas Instruments Incorporated

Inventor： Prasanth Viswanathan Pillai ,  Richard Mark Poley ,  Venkatesh Natarajan ,  Alexander Tessarolo

IPC: G06F7/548

Abstract: In described examples, an apparatus is arranged to generate a linear term, a quadratic term, and a constant term of a transcendental function with, respectively, a first circuit, a second circuit, and a third circuit in response to least significant bits of an input operand and in response to, respectively, a first, a second, and a third table value that is retrieved in response to, respectively, a first, a second, and a third index generated in response to most significant bits of the input operand. The third circuit is further arranged to generate a mantissa of an output operand in response to a sum of the linear term, the quadratic term, and the constant term.

公开(公告)号：US20190286418A1

公开(公告)日：2019-09-19

申请号：US16432257

申请日：2019-06-05

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Alexander Tessarolo ,  Prasanth Viswanathan Pillai ,  Venkatesh Natarajan

IPC: G06F7/535

Abstract: A processor includes a core and a plurality of registers including a first register, a second register, and a third register. The core is configured to perform a division operation that includes execution of a sign extraction instruction in which a sign of at least one of a numerator value and a denominator value is stored, a conditional subtraction instruction which divides the numerator value by the denominator value to generate a quotient value and a remainder value, and a sign assignment instruction which adjusts the sign of at least one of the quotient and remainder values. The conditional subtraction instruction is configured to cause the core to perform multiple iterations of a conditional subtraction in one execution of the conditional subtraction instruction and in one clock cycle. Others methods and apparatus are described as well.

公开(公告)号：US20170033955A1

公开(公告)日：2017-02-02

申请号：US15083549

申请日：2016-03-29

Applicant: Texas Instruments Incorporated

Inventor： Venkatesh Natarajan ,  Alexander Tessarolo

IPC: H04L25/49 ,  H04L5/00 ,  H04L1/00

CPC classification number: H04L25/49 ,  G06F13/4282 ,  H04L1/0041 ,  H04L1/0045 ,  H04L1/0061 ,  H04L1/0083 ,  H04L1/009 ,  H04L1/0091 ,  H04L5/0044 ,  H04L25/0266

Abstract: Methods and apparatus to perform serial communications are disclosed. An example serial data transmitter includes: a clock signal generator to generate a digital clock signal; a clock signal controller to enable the clock signal generator; a line break signal generator to, in response to an expiration of a time period, trigger the transmission of a transmission line check frame; a data integrity check generator to generate error detection data corresponding to first data to be transmitted via the transmission port; a signal framer to: generate a first data frame having a preamble, second data, third data, the first data, the error detection data, and fourth data; and generate the transmission line check frame.

Abstract translation: 公开了执行串行通信的方法和装置。 示例串行数据发送器包括：时钟信号发生器，用于产生数字时钟信号; 时钟信号控制器，用于使能时钟信号发生器; 断线信号发生器响应于时间段的到期触发传输线路检查帧的传输; 数据完整性检查生成器，用于生成与通过传输端口发送的第一数据相对应的错误检测数据; 信号成帧器，用于：产生具有前导码，第二数据，第三数据，第一数据，错误检测数据和第四数据的第一数据帧; 并生成传输线检查帧。

公开(公告)号：US20140129908A1

公开(公告)日：2014-05-08

申请号：US13669447

申请日：2012-11-06

Applicant: TEXAS INSTRUMENTS, INCORPORATED

Inventor： Prohor Chowdhury ,  Alexander Tessarolo

IPC: H03M13/23

CPC classification number: H03M13/4107

Abstract: A decoding system suitable for Viterbi decoding includes a decoder that includes a state metrics array, a butterfly unit, and a constraint length multiplexer. The state metrics array includes registers in which each register is arranged to store a state metric for processing. The butterfly unit includes an array of butterfly elements where each butterfly element is arranged to generate intermediate state metrics in parallel with other butterfly elements in the butterfly unit. The constraint length multiplexer unit is arranged to generate new state metrics in response to the intermediate state metrics and a Viterbi constraint length value stored in a constraint length register. Transition bits can also be generated in response to the constraint length.

Abstract translation: 适用于维特比解码的解码系统包括包括状态度量阵列，蝶形单元和约束长度多路复用器的解码器。 状态度量阵列包括寄存器，其中每个寄存器被布置成存储用于处理的状态度量。 蝶形单元包括一组蝴蝶元件，其中每个蝶形元件被布置成与蝴蝶单元中的其它蝶形元件并行生成中间状态度量。 约束长度多路复用器单元被布置为响应于中间状态度量和存储在约束长度寄存器中的维特比约束长度值来生成新的状态度量。 也可以响应于约束长度来生成转换位。

公开(公告)号：US20240427602A1

公开(公告)日：2024-12-26

申请号：US18603815

申请日：2024-03-13

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Alexander Tessarolo ,  Venkatesh Natarajan

IPC: G06F9/38 ,  G06F9/30

Abstract: Various embodiments of the present disclosure relate to the conditional execution of program code. In an example embodiment, a system including instruction fetch circuitry, decoder circuitry, and multi-condition branch circuitry is provided. The instruction fetch circuitry is configured to fetch a multi-condition branch instruction (MCBI) from memory. The MCBI identifies multiple status registers and multiple branch destinations. The multiple status registers of the MCBI are representative of registers which hold results of multiple condition evaluations, such that each status register corresponds to a different one of the multiple condition evaluations. Similarly, the multiple branch destinations of the MCBI also correspond to a different one of the multiple condition evaluations. The instruction fetch circuitry provides the MCBI to the decoder circuitry. In response, the decoder circuitry is configured to cause the multi-condition branch circuitry to execute the multi-condition branch instruction.

公开(公告)号：US10177747B2

公开(公告)日：2019-01-08

申请号：US15274576

申请日：2016-09-23

Applicant: Texas Instruments Incorporated

Inventor： Alexander Tessarolo ,  Saya Goud Langadi

IPC: G01R23/02 ,  H03K3/03 ,  H03K5/159 ,  H03K19/20

Abstract: A high resolution capture circuit and integrated circuit chip are disclosed and include first and second capture delay lines and an oscillator delay line. The oscillator delay line includes N timing delay elements sequentially coupled in a ring to generate a first clock signal. The first and second capture delay lines each include M capture delay elements sequentially coupled to pass a received signal in a first direction along a first signal path and to pass a clock signal in a second direction opposite to the first direction along a second signal path. The first capture delay line uses the first clock signal and the second capture delay line uses an inverse of the first clock signal. Each capture delay element forms a flip-flop and provides a one-bit output. All delay elements have essentially identical timing and M is equal to either N or to N/2.