公开(公告)号：US20250060887A1

公开(公告)日：2025-02-20

申请号：US18629657

申请日：2024-04-08

Applicant: Texas Instruments Incorporated

Inventor： Prasanth Viswanathan Pillai ,  David Foley ,  Rajasekhar Allu ,  Amrit Mundra ,  Patrick Kruse

IPC: G06F3/06

Abstract: Methods, apparatus, systems, and articles of manufacture are described to facilitate access control in memory. An example method includes accessing state values stored in non-volatile memory, the state values corresponding to a state of the non-volatile memory; responsive to obtaining a request to enter a diagnostic mode, authenticating credentials corresponding to the request; determining the state of the non-volatile memory based on the state values; and determining whether to permit or prohibit access to the non-volatile memory based on the determined state.

公开(公告)号：US20250021242A1

公开(公告)日：2025-01-16

申请号：US18771764

申请日：2024-07-12

Applicant: Texas Instruments Incorporated

Inventor： David Foley ,  Saya Goud Langadi ,  Alexander Tessarolo ,  Venkatesh Natarajan

IPC: G06F3/06

Abstract: In described examples, an integrated circuit (IC) includes a memory and a processor coupled to the memory. The processor is configured to execute a discontinuity instruction, which specifies a memory address, to transition from executing according to a first stack pointer to executing according to a second stack pointer. The first stack pointer is copied from an active stack register to an inactive first stack pointer register. The processor determines whether the specified memory address stores a stack entry instruction that corresponds to the discontinuity instruction. If it does, the second stack pointer is copied from the inactive second stack pointer register to the active stack register, and the processor executes the stack entry instruction and begins execution according to the second stack pointer.

公开(公告)号：US20250021656A1

公开(公告)日：2025-01-16

申请号：US18771795

申请日：2024-07-12

Applicant: Texas Instruments Incorporated

Inventor： David Foley ,  Saya Goud Langadi ,  ALEXANDER TESSAROLO ,  Venkatesh Natarajan

IPC: G06F21/57 ,  G06F21/54 ,  G06F21/60

Abstract: In described examples, a circuit device includes a memory having a set of memory ranges, a logic circuit, access protection registers (APRs), ZONE debug permission registers, and a processor coupled to the memory. Each APR stores memory access permissions for an associated memory range. Each ZONE debug permission register stores debug permissions for a ZONE. Each ZONE is associated with a subset of the APRs so that each APR is associated with one ZONE. The processor executes a debug instruction to control the circuit device as follows. An APR associated with a memory address in the debug instruction provides a first permission to a first logic circuit input. The ZONE debug permission registers provide a second permission responsive to a credential to a second logic circuit input. The processor performs a debug action responsive to the debug instruction and a logic circuit output.

公开(公告)号：US20250021494A1

公开(公告)日：2025-01-16

申请号：US18771733

申请日：2024-07-12

Applicant: Texas Instruments Incorporated

Inventor： David Foley ,  Saya Goud Langadi ,  ALEXANDER TESSAROLO ,  Venkatesh Natarajan

IPC: G06F12/14 ,  G06F9/38

Abstract: In described examples, a circuit device includes a memory having a set of memory ranges and a processor device coupled to the memory. The processor device is configured to fetch programmable instructions from the memory, and configured to determine memory access and execution permissions for the programmable instructions. Permissions are determined responsive to a set of a set of access protection registers (APRs) and a set of LINKs. The APRs each specify permissions for a respective associated memory range. The LINKs are each associated with a respective subset of the APRs. Each of the APRs specifies access protection responsive to each LINK. Each of the programmable instructions corresponds to the APR (source APR) associated with a memory range in which the programmable instruction is stored, and corresponds to the LINK (source LINK) associated with the respective source APR.