公开(公告)号：US20250141382A1

公开(公告)日：2025-05-01

申请号：US18615202

申请日：2024-03-25

Applicant: Texas Instruments Incorporated

Inventor： Alexander Tessarolo

IPC: H02P21/34 ,  H02P21/00 ,  H02P21/10

Abstract: In described examples, a device includes a non-transitory memory and a processor. The memory stores a first instruction. The processor receives the first instruction from the memory. Executing the first instruction causes the processor to perform the following actions. The processor receives a position vector corresponding to a sum of a first component in a first dimension and a second component in a second dimension. The processor compares a magnitude of the first component to a magnitude of the second component, and compares the first component or the second component to zero. And the processor determines a sector in which the position vector is located responsive to the compare actions and a sector layout. In some examples, execution of additional instructions causes the processor to operate a rotational system in response to the determined sector.

公开(公告)号：US20240427597A1

公开(公告)日：2024-12-26

申请号：US18604043

申请日：2024-03-13

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Alexander Tessarolo ,  Venkatesh Natarajan

IPC: G06F9/30 ,  G06F9/38

Abstract: Various embodiments of the present disclosure relate to the conditional execution of program code. In an example embodiment, a system including instruction fetch circuitry, decoder circuitry, and condition aggregation circuitry is provided. The instruction fetch circuitry is configured to fetch a conditional branch instruction (CBI) from memory which identifies multiple register locations and a condition aggregation operation. The condition aggregation operation is representative of an instruction which identifies multiple conditions to be checked. The instruction fetch circuitry provides the CBI to the decoder circuitry. In response, the decoder circuitry is configured to cause the condition aggregation circuitry to perform the multiple conditions checks with respect to values stored in the multiple register locations.

公开(公告)号：US20220214880A1

公开(公告)日：2022-07-07

申请号：US17143989

申请日：2021-01-07

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Saya Goud Langadi ,  Venkatesh Natarajan ,  Alexander Tessarolo

IPC: G06F9/30 ,  G06F9/38 ,  G06F9/48

Abstract: A processor is provided and includes a core that is configured to perform a decode operation on a multi-instruction packet comprising multiple instructions. The decode operation includes receiving the multi-instruction packet that includes first and second instructions. The first instruction includes a primary portion at a fixed first location and a secondary portion. The second instruction includes a primary portion at a fixed second location between the primary portion of the first instruction and the secondary portion of the first instruction. An operational code portion of the primary portion of each of the first and second instructions is accessed and decoded. An instruction packet including the primary and secondary portions of the first instruction is created, and a second instruction packet including the primary portion of the second instruction is created. The first and second instructions packets are dispatched to respective first and second functional units.

公开(公告)号：US09311274B2

公开(公告)日：2016-04-12

申请号：US14056111

申请日：2013-10-17

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Prohor Chowdhury ,  Alexander Tessarolo

IPC: G06F15/00 ,  G06F17/14

CPC classification number: G06F17/142

Abstract: A system includes a memory bank and a control unit. The control unit is configured to perform FFT computations based on Merged radix-2 butterfly calculations by performing FFT computations over N input items, and to access the memory bank for (½×log2N)×(10×log2N) times.

Abstract translation: 系统包括存储体和控制单元。 控制单元被配置为通过对N个输入项执行FFT计算，并且通过对（1/2×log2N）×（10×log2N）倍的存储体进行基于合并的二进制蝶形运算进行FFT计算。

公开(公告)号：US20250021345A1

公开(公告)日：2025-01-16

申请号：US18731132

申请日：2024-05-31

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Alexander Tessarolo ,  Venkatesh Natarajan

IPC: G06F9/445 ,  G06F13/24

Abstract: Various embodiments include systems and methods to provide deterministic execution times for computer processors. In one example, a hardware module may include hardware logic, which is configured to track a value stored in a counter. The hardware module may detect a read or write access request from a processor, determine whether the value stored in the counter has reached a specified value, and then stall the processor using a hardware signal in response thereto. Once the counter reaches the specified value, the hardware logic may then un-stalls the processor using the hardware signal.

公开(公告)号：US20240370261A1

公开(公告)日：2024-11-07

申请号：US18426174

申请日：2024-01-29

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Alexander Tessarolo

IPC: G06F9/30

Abstract: Various embodiments include processors, methods, and computer program products providing pauses for interrupts and shared memory accesses. A processor may decode a machine code instruction, that machine code instruction including a quantity representing a count. As a result of decoding the instruction, the processor may set the value of the count in a status register. While the count is non-zero, the processor may pause servicing interrupts and/or may block another processor from performing operations on a shared memory resource. The processor may decrement the count with each subsequent decoded instruction. Servicing interrupts may be un-paused and/or access to the shared memory resource may be un-blocked once the count reaches zero.

公开(公告)号：US12032966B2

公开(公告)日：2024-07-09

申请号：US17958219

申请日：2022-09-30

Applicant: Texas Instruments Incorporated

Inventor： Alan Davis ,  Venkatesh Natarajan ,  Alexander Tessarolo

IPC: G06F9/38 ,  G06F7/02

CPC classification number: G06F9/3869 ,  G06F7/02

Abstract: A processor with instruction storage configured to store processor instructions, data storage configured to store processor data representing an array, the array including plural data elements, a controller, and an instruction pipeline. The instruction pipeline includes: a load stage circuit configured to load an array element from the data storage, a compare stage circuit configured to compare the array element to a reference value, a store stage circuit configured to store a set of results that includes a result of the comparison of the array element to the reference value, and a loop hit detect stage circuit configured to determine whether any of the set of results is associated with a hit on the reference value.

公开(公告)号：US20210342120A1

公开(公告)日：2021-11-04

申请号：US17378916

申请日：2021-07-19

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Prasanth Viswanathan Pillai ,  Richard Mark Poley ,  Venkatesh Natarajan ,  Alexander Tessarolo

IPC: G06F7/548

Abstract: In described examples, an apparatus is arranged to generate a linear term, a quadratic term, and a constant term of a transcendental function with, respectively, a first circuit, a second circuit, and a third circuit in response to least significant bits of an input operand and in response to, respectively, a first, a second, and a third table value that is retrieved in response to, respectively, a first, a second, and a third index generated in response to most significant bits of the input operand. The third circuit is further arranged to generate a mantissa of an output operand in response to a sum of the linear term, the quadratic term, and the constant term.

公开(公告)号：US08943392B2

公开(公告)日：2015-01-27

申请号：US13669447

申请日：2012-11-06

Applicant: Texas Instruments, Incorporated

Inventor： Prohor Chowdhury ,  Alexander Tessarolo

IPC: H03M13/03

CPC classification number: H03M13/4107

Abstract: A decoding system suitable for Viterbi decoding includes a decoder that includes a state metrics array, a butterfly unit, and a constraint length multiplexer. The state metrics array includes registers in which each register is arranged to store a state metric for processing. The butterfly unit includes an array of butterfly elements where each butterfly element is arranged to generate intermediate state metrics in parallel with other butterfly elements in the butterfly unit. The constraint length multiplexer unit is arranged to generate new state metrics in response to the intermediate state metrics and a Viterbi constraint length value stored in a constraint length register. Transition bits can also be generated in response to the constraint length.

Abstract translation: 适用于维特比解码的解码系统包括包括状态度量阵列，蝶形单元和约束长度多路复用器的解码器。 状态度量阵列包括寄存器，其中每个寄存器被布置成存储用于处理的状态度量。 蝶形单元包括一组蝴蝶元件，其中每个蝶形元件被布置成与蝴蝶单元中的其它蝶形元件并行生成中间状态度量。 约束长度多路复用器单元被布置为响应于中间状态度量和存储在约束长度寄存器中的维特比约束长度值来生成新的状态度量。 也可以响应于约束长度来生成转换位。

公开(公告)号：US12299451B2

公开(公告)日：2025-05-13

申请号：US17897016

申请日：2022-08-26

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： David P. Foley ,  Alexander Tessarolo ,  Alan L. Davis

IPC: G06F9/38 ,  G06F9/30

Abstract: In an example, a system includes a processor, where the processor includes a plurality of processor registers, and where the processor is configured to execute a first instruction in a first execution context. The processor is also configured to receive a PRESERVE instruction that indicates at least one processor register among the plurality of processor registers. The processor is configured to, responsive to the PRESERVE instruction, preserve parameters in the at least one processor register and clear other processor registers in the plurality of processor registers in the first execution context. The processor is also configured to execute a second instruction in a second execution context.