公开(公告)号：US20250080096A1

公开(公告)日：2025-03-06

申请号：US18241080

申请日：2023-08-31

Applicant: Texas Instruments Incorporated

Inventor： Sovan Ghosh ,  Visvesvaraya Appala Pentakota

IPC: H03K5/01 ,  H03M1/12

Abstract: An example apparatus includes programmable circuitry configured to: provide a sample signal, a time amplification (TA) signal, and a kick signal to sample and conversion circuitry; sample a differential signal for a first amount of time-based on the sample signal; charge a first capacitor for a second amount of time-based on the first kick signal; after the first amount of time and the second amount of time, charge a second capacitor, the charging based on the first TA signal, the charging to cause a falling edge in a first delay signal; and generating, a rising edge in the delay signal based on the falling edge of O_RST signal.

公开(公告)号：US11095300B2

公开(公告)日：2021-08-17

申请号：US16904604

申请日：2020-06-18

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Sovan Ghosh ,  Amal Kumar Kundu ,  Janakiraman Seetharaman

IPC: H03K5/24 ,  H03M1/08

Abstract: A comparator circuit includes a first transistor configured to receive a first input and a second transistor configured to receive a second input. The comparator circuit further includes a third transistor coupled to a terminal of each of the first and second transistors. The third transistor is configured to be controlled by a first control signal. A gate of a fifth transistor is coupled to a terminal of a fourth transistor at a first node and a gate of the fourth transistor is coupled to a terminal of the fifth transistor at a second node. A sixth transistor is coupled between the first and fourth transistors. A seventh transistor is coupled between the second and fifth transistors. A gate of the sixth transistor and a gate of the seventh transistor are coupled together at a fixed voltage level.

公开(公告)号：US20200321970A1

公开(公告)日：2020-10-08

申请号：US16904604

申请日：2020-06-18

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Sovan Ghosh ,  Amal Kumar Kundu ,  Janakiraman Seetharaman

IPC: H03M1/08 ,  H03K5/24

Abstract: A comparator circuit includes a first transistor configured to receive a first input and a second transistor configured to receive a second input. The comparator circuit further includes a third transistor coupled to a terminal of each of the first and second transistors. The third transistor is configured to be controlled by a first control signal. A gate of a fifth transistor is coupled to a terminal of a fourth transistor at a first node and a gate of the fourth transistor is coupled to a terminal of the fifth transistor at a second node. A sixth transistor is coupled between the first and fourth transistors. A seventh transistor is coupled between the second and fifth transistors. A gate of the sixth transistor and a gate of the seventh transistor are coupled together at a fixed voltage level.