公开(公告)号：US10819294B1

公开(公告)日：2020-10-27

申请号：US16574231

申请日：2019-09-18

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Sovan Ghosh ,  Amal Kumar Kundu ,  Laxmi Vivek Tripurari ,  Anand Subramanian

IPC: H03F1/56 ,  H04R3/04 ,  H04R3/00

Abstract: A circuit includes first and second gain stages and an output transistor. The second gain stage includes a transconductance amplifier and a variable impedance circuit coupled to an output of the transconductance amplifier. The variable impedance circuit is configured to implement a first impedance level at frequencies below a first frequency threshold and to implement a second impedance level at frequencies above a second frequency level. The first impedance level is larger than the second impedance level. The output transistor has a control input coupled to the variable impedance circuit. At frequencies above the second frequency threshold, the second impedance level is configured to be inversely related to current through the output transistor.

公开(公告)号：US11349492B2

公开(公告)日：2022-05-31

申请号：US17112095

申请日：2020-12-04

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Sovan Ghosh ,  Minkle Eldho Paul ,  Laxmi Vivek Tripurari ,  Amal Kumar Kundu

IPC: H03M1/12 ,  H03M1/46 ,  H03M1/10 ,  H03M1/06 ,  G11C27/02 ,  H03M1/00

Abstract: An analog-to-digital converter (ADC) circuit includes a signal input terminal, a sample-and-hold circuit, and a successive approximation register (SAR) ADC. The sample-and-hold circuit includes an input terminal coupled to the signal input terminal. The SAR ADC includes a comparator, a first capacitive digital-to-analog converter (CDAC), and a second CDAC. The first CDAC includes a first input terminal coupled to the signal input terminal, a second input terminal coupled to an output terminal of the sample-and-hold circuit, and an output terminal coupled to a first input terminal of the comparator. The second CDAC includes a first input terminal coupled to the signal input terminal, an output terminal coupled to a second input terminal of the comparator.

公开(公告)号：US10727852B2

公开(公告)日：2020-07-28

申请号：US16555265

申请日：2019-08-29

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Sovan Ghosh ,  Amal Kumar Kundu ,  Janakiraman Seetharaman

IPC: H03K5/00 ,  H03M1/08 ,  H03K5/24

Abstract: A comparator circuit includes a first transistor configured to receive a first input and a second transistor configured to receive a second input. The comparator circuit further includes a third transistor coupled to a terminal of each of the first and second transistors. The third transistor is configured to be controlled by a first control signal. A gate of a fifth transistor is coupled to a terminal of a fourth transistor at a first node and a gate of the fourth transistor is coupled to a terminal of the fifth transistor at a second node. A sixth transistor is coupled between the first and fourth transistors. A seventh transistor is coupled between the second and fifth transistors. A gate of the sixth transistor and a gate of the seventh transistor are coupled together at a fixed voltage level.

公开(公告)号：US11095300B2

公开(公告)日：2021-08-17

申请号：US16904604

申请日：2020-06-18

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Sovan Ghosh ,  Amal Kumar Kundu ,  Janakiraman Seetharaman

IPC: H03K5/24 ,  H03M1/08

Abstract: A comparator circuit includes a first transistor configured to receive a first input and a second transistor configured to receive a second input. The comparator circuit further includes a third transistor coupled to a terminal of each of the first and second transistors. The third transistor is configured to be controlled by a first control signal. A gate of a fifth transistor is coupled to a terminal of a fourth transistor at a first node and a gate of the fourth transistor is coupled to a terminal of the fifth transistor at a second node. A sixth transistor is coupled between the first and fourth transistors. A seventh transistor is coupled between the second and fifth transistors. A gate of the sixth transistor and a gate of the seventh transistor are coupled together at a fixed voltage level.

公开(公告)号：US20200321970A1

公开(公告)日：2020-10-08

申请号：US16904604

申请日：2020-06-18

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Sovan Ghosh ,  Amal Kumar Kundu ,  Janakiraman Seetharaman

IPC: H03M1/08 ,  H03K5/24

Abstract: A comparator circuit includes a first transistor configured to receive a first input and a second transistor configured to receive a second input. The comparator circuit further includes a third transistor coupled to a terminal of each of the first and second transistors. The third transistor is configured to be controlled by a first control signal. A gate of a fifth transistor is coupled to a terminal of a fourth transistor at a first node and a gate of the fourth transistor is coupled to a terminal of the fifth transistor at a second node. A sixth transistor is coupled between the first and fourth transistors. A seventh transistor is coupled between the second and fifth transistors. A gate of the sixth transistor and a gate of the seventh transistor are coupled together at a fixed voltage level.

公开(公告)号：US20240143522A1

公开(公告)日：2024-05-02

申请号：US17977264

申请日：2022-10-31

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Srijan Rastogi ,  Bharath Singareddy ,  Amal Kumar Kundu ,  Rudravaram Vaishnavi

IPC: G06F13/20 ,  G06F13/38 ,  G06F13/42

CPC classification number: G06F13/20 ,  G06F13/382 ,  G06F13/4282 ,  G06F2213/0042

Abstract: A repeater device includes a packet input and a packet output. A first path extends from the packet input to the packet output. The first path includes a transmitter having a transmitter input coupled to the packet input, a transmitter output coupled to the packet output, and a transmitter enable. A second path extends in parallel with the first path and includes a variable delay circuit. The variable delay circuit has an input coupled to the packet input and an output coupled to the transmitter enable of the transmitter.

公开(公告)号：US10886933B1

公开(公告)日：2021-01-05

申请号：US16656913

申请日：2019-10-18

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Sovan Ghosh ,  Minkle Eldho Paul ,  Laxmi Vivek Tripurari ,  Amal Kumar Kundu

IPC: H03M1/12 ,  H03M1/46 ,  H03M1/10 ,  H03M1/06 ,  G11C27/02 ,  H03M1/00

Abstract: An analog-to-digital converter (ADC) circuit includes a signal input terminal, a sample-and-hold circuit, and a successive approximation register (SAR) ADC. The sample-and-hold circuit includes an input terminal coupled to the signal input terminal. The SAR ADC includes a comparator, a first capacitive digital-to-analog converter (CDAC), and a second CDAC. The first CDAC includes a first input terminal coupled to the signal input terminal, a second input terminal coupled to an output terminal of the sample-and-hold circuit, and an output terminal coupled to a first input terminal of the comparator. The second CDAC includes a first input terminal coupled to the signal input terminal, an output terminal coupled to a second input terminal of the comparator.

公开(公告)号：US10447290B2

公开(公告)日：2019-10-15

申请号：US15837040

申请日：2017-12-11

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Sovan Ghosh ,  Amal Kumar Kundu ,  Janakiraman Seetharaman

IPC: H03K5/00 ,  H03M1/08 ,  H03K5/24

Abstract: A comparator circuit includes a first transistor configured to receive a first input and a second transistor configured to receive a second input. The comparator circuit further includes a third transistor coupled to a terminal of each of the first and second transistors. The third transistor is configured to be controlled by a first control signal. A gate of a fifth transistor is coupled to a terminal of a fourth transistor at a first node and a gate of the fourth transistor is coupled to a terminal of the fifth transistor at a second node. A sixth transistor is coupled between the first and fourth transistors. A seventh transistor is coupled between the second and fifth transistors. A gate of the sixth transistor and a gate of the seventh transistor are coupled together at a fixed voltage level.

公开(公告)号：US11527999B2

公开(公告)日：2022-12-13

申请号：US17027093

申请日：2020-09-21

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Sovan Ghosh ,  Amal Kumar Kundu ,  Laxmi Vivek Tripurari ,  Anand Subramanian

IPC: H03F1/56 ,  H04R3/04 ,  H04R3/00

Abstract: A circuit includes first and second gain stages and an output transistor. The second gain stage includes a transconductance amplifier and a variable impedance circuit coupled to an output of the transconductance amplifier. The variable impedance circuit is configured to implement a first impedance level at frequencies below a first frequency threshold and to implement a second impedance level at frequencies above a second frequency level. The first impedance level is larger than the second impedance level. The output transistor has a control input coupled to the variable impedance circuit. At frequencies above the second frequency threshold, the second impedance level is configured to be inversely related to current through the output transistor.

公开(公告)号：US11206035B2

公开(公告)日：2021-12-21

申请号：US16702090

申请日：2019-12-03

Applicant: Texas Instruments Incorporated

Inventor： Rahul Vijay Kulkarni ,  Shridhar More ,  Amal Kumar Kundu ,  Minkle Eldho Paul

IPC: H03M1/10 ,  H03M1/12 ,  H03M1/46

Abstract: An analog to digital (A/D) converter includes a capacitor array having respective first terminals selectively coupled to a reference voltage or ground via a plurality of switches and having respective second terminals coupled to a sample and hold (S/H) output. The A/D converter also includes a voltage comparator having a first input coupled to the S/H output and having a second input coupled to a bias voltage. The voltage comparator is configured to output a comparison voltage responsive to a sampled charge at the S/H output and the bias voltage. The A/D converter also includes a successive approximation register coupled to receive the comparison voltage and configured to output an approximate digital code responsive to the comparison voltage, wherein the approximate digital code is varied by controlling an equivalent capacitance of the capacitor array.