公开(公告)号：US20100321064A1

公开(公告)日：2010-12-23

申请号：US12486266

申请日：2009-06-17

申请人： Lennart K. Mathe

发明人： Lennart K. Mathe

IPC分类号： H03K19/00 ,  H03M3/00 ,  H03K19/20

CPC分类号： G06F17/5018 ,  G06F2217/84

摘要： A combinatorial circuit with pre-calculation and having shorter delay is described. The combinatorial circuit uses information available from earlier input signals to pre-calculate intermediate signals, which are used to generate output signals when the last input signal arrives. The combinatorial circuit includes an input calculation block, at least one pre-calculation block, and an output calculation block coupled in series. The input calculation block receives some input signals and generates intermediate signals for the first pre-calculation block. The pre-calculation block(s) receive at least one earlier input signal and generate additional intermediate signals. The output calculation block receives the latest input signal and the intermediate signals from the last pre-calculation block and generates the output signals. The pre-calculation block(s) and the output calculation block may be implemented with simple circuits. In another aspect, a delta sigma (ΔΣ) modulator may use the combinatorial circuit with pre-calculation in order to improve operating speed.

摘要翻译： 描述了具有预计算并具有较短延迟的组合电路。 组合电路使用早期输入信号可用的信息来预先计算中间信号，这些信号用于在最后一个输入信号到达时产生输出信号。 组合电路包括输入计算块，至少一个预计算块和串联耦合的输出计算块。 输入计算块接收一些输入信号并产生用于第一预计算块的中间信号。 预计算块接收至少一个较早的输入信号并产生附加的中间信号。 输出计算块从最后一个预计算块接收最新的输入信号和中间信号，并产生输出信号。 预计算块和输出计算块可以用简单的电路来实现。 另一方面，ΔΣ（＆Dgr＆amp; Sgr）调制器可以使用组合电路进行预先计算，以提高操作速度。