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公开(公告)号：US5956324A
公开(公告)日：1999-09-21
申请号：US960775
申请日：1997-10-30
申请人： Thomas L. Engdahl , Paul R. Hartmann , Kevin Pope , Kevin Cadieux
发明人： Thomas L. Engdahl , Paul R. Hartmann , Kevin Pope , Kevin Cadieux
CPC分类号： H04J3/0623 , H04J3/0608 , H04J3/14 , H04M3/22 , H04M3/244
摘要： A DS3 level access, monitor and test system for a telephone network. The system provides selective, and hitless, bit overwrite in any of the embedded DS1, DS0 and subrate channels in a DS3 signal. Multiple DS0 and subrate channels can be tested via the asynchronous time slot interchange in conjunction with the recombiner of the present invention. The present invention further includes a lookahead reframer for framing to the DS3 signal. The present invention also includes a facilities data link (FDL) handler for capturing the FDL channel data in every DS1 channel in a DS3 signal. A high speed bit-for-bit compare is interfaced to a protect path to provide 1:1 fault protection in the system of the present invention. Full time performance monitoring on DS1 and DS3 signals is performed by a shared resource. The system of the present invention provides an integrated approach to synchronization measurement and relative synchronization.
摘要翻译： 用于电话网络的DS3级别访问，监视和测试系统。 该系统在DS3信号中的任何嵌入式DS1，DS0和子速率通道中提供选择性和无中断位重写。 可以通过与本发明的重组器结合的异步时隙交换来测试多个DS0和子速率信道。 本发明还包括用于对DS3信号进行成帧的前瞻性重写器。 本发明还包括用于在DS3信号中的每个DS1信道中捕获FDL信道数据的设施数据链路（FDL）处理程序。 与本发明的系统中提供1：1故障保护的保护路径相连接的高速比特比较比较。 DS1和DS3信号的全时性能监控由共享资源执行。 本发明的系统提供了同步测量和相对同步的综合方法。
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公开(公告)号：US5602828A
公开(公告)日：1997-02-11
申请号：US451686
申请日：1995-05-26
申请人： Thomas L. Engdahl , Paul R. Hartmann , Kevin Pope , Kevin Cadieux
发明人： Thomas L. Engdahl , Paul R. Hartmann , Kevin Pope , Kevin Cadieux
CPC分类号： H04J3/0623 , H04J3/0608 , H04J3/14 , H04M3/22 , H04M3/244
摘要： A DS3 level access, monitor and test system for a telephone network. The system provides selective, and hitless, bit overwrite in any of the embedded DS1, DS0 and subrate channels in a DS3 signal. Multiple DS0 and subrate channels can be tested via the asynchronous time slot interchange in conjunction with the recombiner of the present invention. The present invention further includes a lookahead reframer for framing to the DS3 signal. The present invention also includes a facilities data link (FDL) handler for capturing the FDL channel data in every DS1 channel in a DS3 signal. A high speed bit-for-bit compare is interfaced to a protect path to provide 1:1 fault protection in the system of the present invention. Full time performance monitoring on DS1 and DS3 signals is performed by a shared resource. The system of the present invention provides an integrated approach to synchronization measurement and relative synchronization.
摘要翻译： 用于电话网络的DS3级别访问，监视和测试系统。 该系统在DS3信号中的任何嵌入式DS1，DS0和子速率通道中提供选择性和无中断位重写。 可以通过与本发明的重组器结合的异步时隙交换来测试多个DS0和子速率信道。 本发明还包括用于对DS3信号进行成帧的前瞻性重写器。 本发明还包括用于在DS3信号中的每个DS1信道中捕获FDL信道数据的设施数据链路（FDL）处理程序。 与本发明的系统中提供1：1故障保护的保护路径相连接的高速比特比较比较。 DS1和DS3信号的全时性能监控由共享资源执行。 本发明的系统提供了同步测量和相对同步的综合方法。
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13.发明授权Digital signal comparison circuit in a performance monitoring and test system 失效数字信号比较电路在性能监测和测试系统中
公开(公告)号：US5581228A
公开(公告)日：1996-12-03
申请号：US451170
申请日：1995-05-26
申请人： Kevin Cadieux , Paul R. Hartmann , Kevin Pope
发明人： Kevin Cadieux , Paul R. Hartmann , Kevin Pope
CPC分类号： H04J3/0623 , H04J3/0608 , H04J3/14 , H04M3/22 , H04M3/244
摘要： A DS3 level access, monitor and test system including a digital comparator for a telephone network. A high speed bit-for-bit compare is interfaced to a protect path to provide 1:1 fault protection in the system of the present invention. Full time performance monitoring on DS1 and DS3 signals is performed by a shared resource. The system of the present invention provides an integrated approach to synchronization measurement and relative synchronization.
摘要翻译： DS3级接入，监控和测试系统，包括电话网络的数字比较器。 与本发明的系统中提供1：1故障保护的保护路径相连接的高速比特比较比较。 DS1和DS3信号的全时性能监控由共享资源执行。 本发明的系统提供了同步测量和相对同步的综合方法。
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