Abstract:
An echo canceller and an echo cancellation method are provided. In the echo cancellation method, a transmitting data sequence is received, and M taps are provided accordingly. In addition, the M taps are received, and N taps are output according to an echo distribution information, in which the M and N are natural numbers, and M>N. Besides, the N taps are multiplied by N tap coefficients respectively to generate N products. Further, the N products are summed up to generate an echo cancellation signal. Thereby, the cost of the echo cancellation is decreased.
Abstract:
A transceiver apparatus, a receiver and a power saving method thereof are provided. The receiver includes an analog-to-digital converter, an equalizer, a slicer, a delay unit, a decoder, a select unit and a control unit. The analog-to-digital converter transforms a received signal into a digital signal. The equalizer adjusts the digital signal to generate an equalized signal. The slicer receives and slices the equalized signal and generates a sliced signal. The delay unit delays the sliced signal. The decoder determines whether to decode the equalized signal or not according the control signal. The select unit selects one of the output of the delayed sliced signal and the output of the decoder to be an output signal according to a second control signal. The control unit determines whether to enable the control signal and the second control signal according to the state of the sliced signal and the output signal.
Abstract:
A novel physical layer circuit enables the computer equipments in connection with the invented physical layer circuit to transmit and to receive data through the telephone cord. The physical layer circuit may be provided in a network interface chipset and comprises an encoder circuit, a transmitter circuit, a receiving filter, an analog to digital converter, a clock signal generator and a decoder circuit. The present invention also discloses the network interface chipset that contains the physical layer circuit, the local area communications system using the network interface chipset.
Abstract:
A network transmitting apparatus and a power saving method thereof are provided. The network transmitting apparatus includes a chip, a transformer, and a power regulating unit. The chip includes a detecting and controlling unit, an analog circuit, and a digital circuit. The detecting and controlling unit receives a received signal and detects the received signal and a state of the chip to generate a first control signal. The transformer has a first side coupled to the chip and a second side. The power regulating unit coupled to the detecting and controlling unit and a center tap of the first side of the transformer is used for receiving a voltage, generating a first regulated voltage according to the first control signal, and connecting the first regulated voltage to the center tap of the first side of the transformer, the analog circuit, and the digital circuit.
Abstract:
A line transceiver apparatus for multiple transmission standards including a operational amplifier (OP-AMP), a transformer unit, a first variable resistor unit to a sixth variable resistor unit, and a variable resistor control unit is provided. The first resistor and the second resistor are coupled between transmission nodes of the line transceiver apparatus and input nodes of the OP-AMP, and the load nodes of the transformer unit are receiving nodes of the line transceiver apparatus. The variable resistor control unit adjusts the impedances of the first variable resistor unit to the sixth variable resistor unit according to a transmission standard selection signal so as to enable the line transceiver apparatus to support multiple transmission standards.
Abstract:
A network transmitting apparatus and a power saving method thereof are provided. The network transmitting apparatus includes a chip, a transformer, and a power regulating unit. The chip includes a detecting and controlling unit, an analog circuit, and a digital circuit. The detecting and controlling unit receives a received signal and detects the received signal and a state of the chip to generate a first control signal. The transformer has a first side coupled to the chip and a second side. The power regulating unit coupled to the detecting and controlling unit and a center tap of the first side of the transformer is used for receiving a voltage, generating a first regulated voltage according to the first control signal, and connecting the first regulated voltage to the center tap of the first side of the transformer, the analog circuit, and the digital circuit.
Abstract:
An echo canceller and an echo cancellation method are provided. In the echo cancellation method, a transmitting data sequence is received, and M taps are provided accordingly. In addition, the M taps are received, and N taps are output according to an echo distribution information, in which the M and N are natural numbers, and M>N. Besides, the N taps are multiplied by N tap coefficients respectively to generate N products. Further, the N products are summed up to generate an echo cancellation signal. Thereby, the cost of the echo cancellation is decreased.
Abstract:
A transceiver and an echo cancellation method are disclosed. The echo cancellation method includes producing an echo cancellation signal according to a transmission signal; adjusting the amplitude, the delay time or a combination of the amplitude and the delay time of the echo cancellation signal according to an adjusting parameter; receiving an echo signal derived from the transmission signal and performing a subtraction operation on the echo signal by using the echo cancellation signal so as to obtain an echo residual; and producing the adjusting parameter according to the echo residual. The provided method can effectively reduce the interference caused by the echo signal.
Abstract:
A DC wander canceling device is provided for canceling DC wander. The DC wander canceling device comprises an analog front end, an equalizer, a slicer, and a digital/analog DC wander canceller. The digital/analog DC wander canceller is coupled to the slicer and the analog front end for receiving a sliced signal. According to the difference of the received sliced signal and the input signal of the slicer, the digital/analog DC wander canceller compensates the equalized signal to cancel a digital DC wander, and also cancel an analog DC wander at the input of the analog front end, to enhance the accuracy of signal demodulation.