公开(公告)号：US20230352478A1

公开(公告)日：2023-11-02

申请号：US18218578

申请日：2023-07-05

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chang-Po Hsiung ,  Ching-Chung Yang ,  Shan-Shi Huang ,  Wen-Fang Lee

IPC: H01L27/085

CPC classification number: H01L27/085

Abstract: A semiconductor structure comprises a substrate having a first well region of a first conductive type, a second well region of a second conductive type, and a junction between the first well region and the second well region. The first conductive type and the second conductive type are complementary. A plurality of first dummy structures and second dummy structures and at least a first active region are defined in the first well region by an isolation structure. The first dummy structures are adjacent to the junction and respectively comprise a first metal silicide region and a first doped region of the first conductive type and between the first metal silicide region and the first well region. The first dummy structures are between the second dummy structures and the junction. The second dummy structures respectively comprise a second metal silicide region that direct contacts the first well region.

公开(公告)号：US11735586B2

公开(公告)日：2023-08-22

申请号：US17163544

申请日：2021-01-31

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chang-Po Hsiung ,  Ching-Chung Yang ,  Shan-Shi Huang ,  Wen-Fang Lee

IPC: H01L27/085

CPC classification number: H01L27/085

Abstract: A semiconductor structure is disclosed. The semiconductor structure includes a substrate, a first well region of a first conductive type and a second well region of a second conductive type disposed in the substrate. The first conductive type and the second conductive type are complementary. A plurality of first dummy structures are disposed in the first well region and arranged along a junction between the first well region and the second well region. The first dummy structures respectively include a first conductive region and a first doped region disposed between the first conductive region and the first doped region.

公开(公告)号：US20220208760A1

公开(公告)日：2022-06-30

申请号：US17163544

申请日：2021-01-31

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chang-Po Hsiung ,  Ching-Chung Yang ,  Shan-Shi Huang ,  Wen-Fang Lee

IPC: H01L27/085

Abstract: A semiconductor structure is disclosed. The semiconductor structure includes a substrate, a first well region of a first conductive type and a second well region of a second conductive type disposed in the substrate. The first conductive type and the second conductive type are complementary. A plurality of first dummy structures are disposed in the first well region and arranged along a junction between the first well region and the second well region. The first dummy structures respectively include a first conductive region and a first doped region disposed between the first conductive region and the first doped region.

公开(公告)号：US09397084B1

公开(公告)日：2016-07-19

申请号：US14636122

申请日：2015-03-02

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shin-Hung Li ,  Fan-Chi Meng ,  Shan-Shi Huang

IPC: H01L27/02 ,  H01L21/822 ,  H01L23/528 ,  H01L23/50 ,  H01L29/66 ,  H01L23/00 ,  H01L21/768

CPC classification number: H01L27/0255 ,  H01L24/11 ,  H01L24/13 ,  H01L24/43 ,  H01L24/45 ,  H01L27/0296 ,  H01L29/66136 ,  H01L29/861 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/48463 ,  H01L2924/00014 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099

Abstract: A structure of ESD protection circuits on a BEOL layer includes a substrate. A plurality of interconnect layers and an inter-level dielectric layer are disposed on the substrate. The inter-level dielectric layer is disposed between the plurality of interconnect layers. The last layer of the interconnect layers comprises an I/O pad, a first pad and a second pad. A first diode and a second diode are disposed on the last layer of the inter-level dielectric layer, wherein the first diode electrically connects to the I/O pad and the first pad and the second diode electrically connects to the I/O pad and the second pad.

Abstract translation: BEOL层上的ESD保护电路的结构包括基板。 多个互连层和层间电介质层设置在基板上。 层间电介质层设置在多个互连层之间。 互连层的最后一层包括I / O焊盘，第一焊盘和第二焊盘。 第一二极管和第二二极管设置在层间电介质层的最后一层上，其中第一二极管电连接到I / O焊盘，第一焊盘和第二二极管电连接到I / O焊盘， 第二垫。