公开(公告)号：US10055288B2

公开(公告)日：2018-08-21

申请号：US15225846

申请日：2016-08-02

Applicant: VIA Technologies, Inc.

Inventor： Ying Yu Tai ,  Jiin Lai ,  Jiangli Zhu

IPC: H03M13/00 ,  G06F11/10 ,  G06F3/06 ,  G11C16/04 ,  G11C29/04

CPC classification number: G06F11/1072 ,  G06F3/0608 ,  G06F3/061 ,  G06F3/0619 ,  G06F3/064 ,  G06F3/0688 ,  G06F11/1068 ,  G11C16/0483 ,  G11C2029/0409 ,  G11C2029/0411

Abstract: A controller device and an operation method for a non-volatile memory with 3-dimensional architecture are provided. The controller device includes an error checking and correcting (ECC) circuit and a controller. The controller is coupled to the non-volatile memory and the ECC circuit. The controller may access a target wordline of the non-volatile memory in accordance with a physical address. The controller groups a plurality of wordlines of the non-volatile memory into a plurality of wordline groups, wherein different wordline groups have different codeword structures. The controller controls the ECC circuit according to the codeword structure of the wordline group of the target wordline, and the ECC circuit generates a codeword to be stored in the target wordline or check a codeword from the target wordline under control of the controller.

公开(公告)号：US20170212801A1

公开(公告)日：2017-07-27

申请号：US15225846

申请日：2016-08-02

Applicant: VIA Technologies, Inc.

Inventor： Ying Yu Tai ,  Jiin Lai ,  Jiangli Zhu

IPC: G06F11/10 ,  G11C29/52 ,  G06F3/06 ,  G11C16/04

CPC classification number: G06F11/1072 ,  G06F3/0608 ,  G06F3/061 ,  G06F3/0619 ,  G06F3/064 ,  G06F3/0688 ,  G06F11/1068 ,  G11C16/0483 ,  G11C2029/0409 ,  G11C2029/0411

Abstract: A controller device and an operation method for a non-volatile memory with 3-dimensional architecture are provided. The controller device includes an error checking and correcting (ECC) circuit and a controller. The controller is coupled to the non-volatile memory and the ECC circuit. The controller may access a target wordline of the non-volatile memory in accordance with a physical address. The controller groups a plurality of wordlines of the non-volatile memory into a plurality of wordline groups, wherein different wordline groups have different codeword structures. The controller controls the ECC circuit according to the codeword structure of the wordline group of the target wordline, and the ECC circuit generates a codeword to be stored in the target wordline or check a codeword from the target wordline under control of the controller.

公开(公告)号：US20180101314A1

公开(公告)日：2018-04-12

申请号：US15287743

申请日：2016-10-07

Applicant: VIA Technologies, Inc.

Inventor： Ying-Yu Tai ,  Jiangli Zhu ,  Jiin Lai

IPC: G06F3/06 ,  G06F12/1009

Abstract: A non-volatile memory (NVM) apparatus and an address classification method thereof are provided. The NVM apparatus includes a NVM and a controller. The controller accesses the NVM in accordance with a write command of a host. The controller may perform the address classification method. The address classification method includes: providing a data look-up table, wherein the data look-up table includes a plurality of data entries, each of the data entries includes a logical address information, a counter value and a timer value; searching the data look-up table based on the logical address of the write command in order to obtain a corresponding counter value and a corresponding timer value; and determining whether the logical address of the write command is a hot data address based on the corresponding counter value and the corresponding timer value.