公开(公告)号：US07853901B2

公开(公告)日：2010-12-14

申请号：US12109501

申请日：2008-04-25

申请人： Viswanathan Lakshmanan ,  Thomas R. O'Brien ,  Richard D. Blinne

发明人： Viswanathan Lakshmanan ,  Thomas R. O'Brien ,  Richard D. Blinne

IPC分类号： G06F17/50

CPC分类号： G06F17/5068

摘要： A method for producing a family of digital integrated circuit designs, where the family has a highest level design and at least one lower level design. The highest level design is first produced. Then, in a programmed computing system without user intervention, the highest level design is automatically processed to selectively remove at least one predetermined metal layer. A closest remaining overlying layer to the at least one removed metal layer is automatically mapped to a closest remaining underlying layer to the at least one removed metal layer, thereby producing the at least one lower level design.

摘要翻译： 一种用于生产数字集成电路设计系列的方法，其中家族具有最高级别的设计和至少一个较低级别的设计。 最高水平的设计是首次生产。 然后，在没有用户干预的编程计算系统中，自动处理最高级别的设计以选择性地移除至少一个预定的金属层。 至少一个去除的金属层的最近的剩余覆盖层被自动映射到至少一个移除的金属层的最接近的剩余的下层，由此产生至少一个较低级设计。

公开(公告)号：US20090271755A1

公开(公告)日：2009-10-29

申请号：US12109501

申请日：2008-04-25

申请人： Viswanathan Lakshmanan ,  Thomas R. O'Brien ,  Richard D. Blinne

发明人： Viswanathan Lakshmanan ,  Thomas R. O'Brien ,  Richard D. Blinne

IPC分类号： G06F17/50

CPC分类号： G06F17/5068

摘要： A method for producing a family of digital integrated circuit designs, where the family has a highest level design and at least one lower level design. The highest level design is first produced. Then, in a programmed computing system without user intervention, the highest level design is automatically processed to selectively remove at least one predetermined metal layer. A closest remaining overlying layer to the at least one removed metal layer is automatically mapped to a closest remaining underlying layer to the at least one removed metal layer, thereby producing the at least one lower level design.

摘要翻译： 一种用于生产数字集成电路设计系列的方法，其中家族具有最高级别的设计和至少一个较低级别的设计。 最高水平的设计是首次生产。 然后，在没有用户干预的编程计算系统中，自动处理最高级别的设计以选择性地移除至少一个预定的金属层。 至少一个去除的金属层的最近的剩余覆盖层被自动映射到至少一个移除的金属层的最接近的剩余的下层，由此产生至少一个较低级设计。

公开(公告)号：US20090051006A1

公开(公告)日：2009-02-26

申请号：US11843768

申请日：2007-08-23

申请人： Richard T. Schultz ,  Thomas R. O'Brien ,  Viswanathan Lakshmanan ,  David M. Ratchkov ,  Stefan G. Block

发明人： Richard T. Schultz ,  Thomas R. O'Brien ,  Viswanathan Lakshmanan ,  David M. Ratchkov ,  Stefan G. Block

IPC分类号： H01G4/40

CPC分类号： H01G4/40

摘要： A decoupling circuit disposed between a first rail and a second rail, where a third power rail is disposed between the first and second rails. A resistor having a first electrode and a second electrode is disposed between the first and second rails. Two capacitors are disposed between the first and second rails. The resistor is connected to the third rail and the two capacitors. In this manner, the two capacitors are connected in series with respect to the resistor, and in parallel with respect to one another. A first of the two capacitors is connected to the first rail, and a second of the two capacitors is connected to the second rail. At least one of the resistor and the two capacitors is disposed at least in part beneath the third rail.

摘要翻译： 设置在第一轨道和第二轨道之间的去耦电路，其中第三电力轨设置在第一和第二轨道之间。 具有第一电极和第二电极的电阻器设置在第一和第二导轨之间。 两个电容器设置在第一和第二导轨之间。 电阻器连接到第三导轨和两个电容器。 以这种方式，两个电容器相对于电阻器串联连接，并且彼此并联。 两个电容器中的第一个连接到第一导轨，并且两个电容器中的第二个连接到第二导轨。 电阻器和两个电容器中的至少一个至少部分地设置在第三导轨下方。

公开(公告)号：US20060064656A1

公开(公告)日：2006-03-23

申请号：US10947498

申请日：2004-09-22

申请人： Viswanathan Lakshmanan ,  Alan Holesovsky ,  Lisa Miller ,  Jonathan Kuppinger

发明人： Viswanathan Lakshmanan ,  Alan Holesovsky ,  Lisa Miller ,  Jonathan Kuppinger

IPC分类号： G06F17/50 ,  G06F9/45

CPC分类号： G06F17/5081

摘要： A method and computer program product for early physical design validation and identification of texted metal short circuits in an integrated circuit design includes steps of: (a) receiving as input a representation of an integrated circuit design; (b) receiving as input a physical design rule deck that specifies rule checks to be performed on the integrated circuit design; (c) generating a specific rule deck from the physical design rule deck wherein the specific rule deck includes only physical design rules that are specific to one of identifying texted metal short circuits in the integrated circuit design and power distribution and input/output cell placement in the integrated circuit design; and (d) performing a physical design validation on the integrated circuit design from the specific rule deck.

摘要翻译： 用于集成电路设计中的短信金属短路的早期物理设计验证和识别的方法和计算机程序产品包括以下步骤：（a）作为输入接收集成电路设计的表示; （b）作为输入接收指定要在集成电路设计上执行的规则检查的物理设计规则卡; （c）从物理设计规则甲板生成特定规则甲板，其中特定规则甲板仅包括专用于识别集成电路设计中的发短信的金属短路和电力分配以及输入/输出电池放置之一的物理设计规则 集成电路设计; 和（d）从特定的规则层面对集成电路设计进行物理设计验证。

公开(公告)号：US20050235234A1

公开(公告)日：2005-10-20

申请号：US10828408

申请日：2004-04-19

申请人： Viswanathan Lakshmanan ,  Richard Blinne ,  Jonathan Kuppinger

发明人： Viswanathan Lakshmanan ,  Richard Blinne ,  Jonathan Kuppinger

IPC分类号： G06F17/50

CPC分类号： G06F17/5022 ,  G06F17/5045

摘要： A method and computer program product for verifying an incremental change to an integrated circuit design are described that include steps of: (a) receiving as input an integrated circuit design database; (b) receiving as input an engineering change order; (c) identifying and marking objects in the integrated circuit design database to indicate a current state of the integrated circuit design database; (d) applying the engineering change order to the integrated circuit design database; (e) analyzing the integrated circuit design database to generate a list of incremental changes to the integrated circuit design database resulting from the engineering change order; (f) identifying and marking objects in the integrated circuit design database included in the list of incremental changes to distinguish objects in the integrated circuit design database that were changed from the current state; and (g) streaming out the integrated circuit design database.

摘要翻译： 描述了用于验证集成电路设计的增量变化的方法和计算机程序产品，其包括以下步骤：（a）作为输入接收集成电路设计数据库; （b）接收工程变更单作为输入; （c）识别和标记集成电路设计数据库中的对象，以指示集成电路设计数据库的当前状态; （d）将工程变更单应用于集成电路设计数据库; （e）分析集成电路设计数据库，以生成由工程变更订单产生的对集成电路设计数据库的增量变化的列表; （f）识别和标记增量变化列表中集成电路设计数据库中的对象，以区分从当前状态改变的集成电路设计数据库中的对象; 和（g）流出集成电路设计数据库。

公开(公告)号：US06775811B2

公开(公告)日：2004-08-10

申请号：US10151826

申请日：2002-05-22

申请人： Viswanathan Lakshmanan ,  Michael Josephides ,  Tom R. O'Brien ,  David A. Morgan

发明人： Viswanathan Lakshmanan ,  Michael Josephides ,  Tom R. O'Brien ,  David A. Morgan

IPC分类号： G06F1750

CPC分类号： G06F17/5072

摘要： A method of circuit design for designing integrated circuits with one or more embedded memories. A placement is generated for timing critical logic associated with each included embedded memory in a logic design. An augmented memory boundary is generated for said each included memory. Each augmented memory boundary encompasses one embedded memory and associated said timing critical logic.

摘要翻译： 一种用于设计具有一个或多个嵌入存储器的集成电路的电路设计方法。 在逻辑设计中生成与每个包含的嵌入式存储器相关联的定时关键逻辑的布局。 为所述每个包括的存储器生成增强的存储器边界。 每个增强的存储器边界包括一个嵌入式存储器和相关联的所述定时关键逻辑。

公开(公告)号：US07829973B2

公开(公告)日：2010-11-09

申请号：US11843768

申请日：2007-08-23

申请人： Richard T. Schultz ,  Thomas R. O'Brien ,  Viswanathan Lakshmanan ,  David M. Ratchkov ,  Stefan G. Block

发明人： Richard T. Schultz ,  Thomas R. O'Brien ,  Viswanathan Lakshmanan ,  David M. Ratchkov ,  Stefan G. Block

IPC分类号： H01G4/40

CPC分类号： H01G4/40

摘要： A decoupling circuit disposed between a first rail and a second rail, where a third power rail is disposed between the first and second rails. A resistor having a first electrode and a second electrode is disposed between the first and second rails. Two capacitors are disposed between the first and second rails. The resistor is connected to the third rail and the two capacitors. In this manner, the two capacitors are connected in series with respect to the resistor, and in parallel with respect to one another. A first of the two capacitors is connected to the first rail, and a second of the two capacitors is connected to the second rail. At least one of the resistor and the two capacitors is disposed at least in part beneath the third rail.

摘要翻译： 设置在第一轨道和第二轨道之间的去耦电路，其中第三电力轨设置在第一和第二轨道之间。 具有第一电极和第二电极的电阻器设置在第一和第二导轨之间。 两个电容器设置在第一和第二导轨之间。 电阻器连接到第三导轨和两个电容器。 以这种方式，两个电容器相对于电阻器串联连接，并且彼此并联。 两个电容器中的第一个连接到第一导轨，并且两个电容器中的第二个连接到第二导轨。 电阻器和两个电容器中的至少一个至少部分地设置在第三导轨下方。

公开(公告)号：US20100070936A1

公开(公告)日：2010-03-18

申请号：US12211238

申请日：2008-09-16

申请人： Viswanathan Lakshmanan ,  Michael Josephides ,  Lisa M. Miller

发明人： Viswanathan Lakshmanan ,  Michael Josephides ,  Lisa M. Miller

IPC分类号： G06F17/50

CPC分类号： G06F17/5081

摘要： A method of waiving verification failures is disclosed. The method generally includes the steps of (A) generating a plurality of circuit error files by performing a plurality of physical verifications on a plurality of circuit designs, the circuit error files containing a plurality of circuit errors of the circuit designs, (B) generating a system error file by performing an additional physical verification on a system design, the system error file containing a plurality of system errors of the system design, the system design incorporating the circuit designs, (C) generating a valid error file by removing the circuit errors from the system error file, the valid error file containing a plurality of valid errors comprising a subset of the system errors and (D) storing the valid error file in a recording medium.

摘要翻译： 公开了一种放弃验证失败的方法。 该方法通常包括以下步骤：（A）通过在多个电路设计上执行多个物理验证来产生多个电路错误文件，所述电路错误文件包含电路设计的多个电路错误，（B）产生 系统错误文件，通过对系统设计进行附加物理验证，系统错误文件包含系统设计的多个系统错误，包含电路设计的系统设计，（C）通过去除电路来生成有效的错误文件 来自系统错误文件的错误，包含多个有效错误的有效错误文件，包括系统错误的子集，以及（D）将有效的错误文件存储在记录介质中。

公开(公告)号：US07480878B2

公开(公告)日：2009-01-20

申请号：US11321260

申请日：2005-12-29

申请人： Alan Lee Holesovsky ,  Viswanathan Lakshmanan ,  Brent Wray Acott

发明人： Alan Lee Holesovsky ,  Viswanathan Lakshmanan ,  Brent Wray Acott

IPC分类号： G06F17/50

CPC分类号： G06F17/5081

摘要： A method and system for validating selected layers of an integrated circuit design. A rundeck is edited to include IC layers and device structures of interest that may require validation. In some embodiments the IC layer of interest may include only metal. A layout versus schematic (LVS) comparison is performed using the edited rundeck and an error report is generated.

摘要翻译： 一种用于验证集成电路设计的选定层的方法和系统。 编辑了一个破损，以包括可能需要验证的感兴趣的IC层和设备结构。 在一些实施例中，感兴趣的IC层可以仅包括金属。 使用编辑后的rundeck执行布局与原理图（LVS）比较，并生成错误报告。

公开(公告)号：US07302654B2

公开(公告)日：2007-11-27

申请号：US10977386

申请日：2004-10-29

申请人： Viswanathan Lakshmanan ,  Michael Josephides ,  Richard D. Blinne

发明人： Viswanathan Lakshmanan ,  Michael Josephides ,  Richard D. Blinne

IPC分类号： G06F17/50

CPC分类号： G06F17/5081

摘要： A method and computer program product for automatically correcting errors in an integrated circuit design includes steps of: (a) performing a physical design validation of an integrated circuit design to verify compliance with a set of design rules; (b) generating a results database of design rule violations detected by the physical design validation; (c) identifying locations in the integrated circuit design from the results database for making design corrections according to a post-processing rule deck so that the locations of the design corrections comply with the set of design rules; and (d) implementing the design corrections in the integrated circuit design.

摘要翻译： 一种用于自动校正集成电路设计中的错误的方法和计算机程序产品包括以下步骤：（a）执行集成电路设计的物理设计验证以验证是否符合一组设计规则; （b）生成通过物理设计验证检测到的设计规则违规的结果数据库; （c）从结果数据库中识别集成电路设计中的位置，以便根据后处理规则表进行设计更正，使设计更正的位置符合设计规则集; 和（d）在集成电路设计中实现设计校正。