公开(公告)号：US20060136855A1

公开(公告)日：2006-06-22

申请号：US11015123

申请日：2004-12-17

申请人： Jason Hoff ,  Viswanathan Lakshmanan ,  Michael Josephides ,  Daniel Prevedel ,  Richard Blinne ,  Jonathan Kuppinger

发明人： Jason Hoff ,  Viswanathan Lakshmanan ,  Michael Josephides ,  Daniel Prevedel ,  Richard Blinne ,  Jonathan Kuppinger

IPC分类号： G06F17/50 ,  G06F9/455

CPC分类号： G06F17/5045 ,  G06F17/5068 ,  G06F2217/04

摘要： A method of implementing an engineering change order includes steps of: (a) receiving as input an integrated circuit design; (b) receiving as input an engineering change order to the integrated circuit design; (c) creating at least one window in the integrated circuit design that encloses a change to the integrated circuit design introduced by the engineering change order wherein the window is bounded by coordinates that define an area that is less than an entire area of the integrated circuit design; (d) performing a routing of the integrated circuit design that excludes routing of any net that is not enclosed by the window; (e) replacing an area in a copy of the integrated circuit design that is bounded by the coordinates of the window with results of the incremental routing to generate a revised integrated circuit design; and (f) generating as output the revised integrated circuit design.

摘要翻译： 一种实现工程变更订单的方法包括以下步骤：（a）接收作为输入的集成电路设计; （b）作为输入接收集成电路设计的工程变更订单; （c）在集成电路设计中创建至少一个窗口，其包围由工程改变顺序引入的集成电路设计的变化，其中窗口由限定小于集成电路的整个区域的区域的坐标界定 设计; （d）执行集成电路设计的路由，该路由排除不包括窗口的任何网络的路由; （e）将由窗口坐标限定的集成电路设计的副本中的区域替换为增量路由的结果以生成修订的集成电路设计; 和（f）产生经修订的集成电路设计的输出。

公开(公告)号：US20050097488A1

公开(公告)日：2005-05-05

申请号：US10697357

申请日：2003-10-29

申请人： Viswanathan Lakshmanan ,  Richard Blinne ,  Jonathan Kuppinger

发明人： Viswanathan Lakshmanan ,  Richard Blinne ,  Jonathan Kuppinger

IPC分类号： G06F9/45 ,  G06F17/50

CPC分类号： G06F17/5081

摘要： A method of partitioning an integrated circuit design for physical design verification includes steps of: (a) receiving as input a representation of an integrated circuit design having a number of physical design layers; (b) receiving as input a composite run deck specifying rule checks to be performed on the integrated circuit design; (c) partitioning the composite run deck into partitioned run decks so that the number of physical design layers referenced by each of the partitioned run decks is a minimum; (d) parsing the representation of the integrated circuit design to filter only the physical design layers required for each of the partitioned run decks into a filtered data deck for each of the partitioned run decks; and (e) generating as output the filtered data deck for each of the partitioned run decks.

摘要翻译： 对用于物理设计验证的集成电路设计进行分区的方法包括以下步骤：（a）作为输入接收具有多个物理设计层的集成电路设计的表示; （b）作为输入接收要在集成电路设计上执行的规则检查的复合运行平台; （c）将复合运行甲板划分为分区运行甲板，使得由每个分区运行甲板引用的物理设计层的数量是最小的; （d）解析集成电路设计的表示，以仅将每个分区运行平台所需的物理设计层过滤成用于每个分区运行平台的过滤数据卡; 和（e）生成用于每个分区运行平台的经过滤数据卡的输出。

公开(公告)号：US20050235234A1

公开(公告)日：2005-10-20

申请号：US10828408

申请日：2004-04-19

申请人： Viswanathan Lakshmanan ,  Richard Blinne ,  Jonathan Kuppinger

发明人： Viswanathan Lakshmanan ,  Richard Blinne ,  Jonathan Kuppinger

IPC分类号： G06F17/50

CPC分类号： G06F17/5022 ,  G06F17/5045

摘要： A method and computer program product for verifying an incremental change to an integrated circuit design are described that include steps of: (a) receiving as input an integrated circuit design database; (b) receiving as input an engineering change order; (c) identifying and marking objects in the integrated circuit design database to indicate a current state of the integrated circuit design database; (d) applying the engineering change order to the integrated circuit design database; (e) analyzing the integrated circuit design database to generate a list of incremental changes to the integrated circuit design database resulting from the engineering change order; (f) identifying and marking objects in the integrated circuit design database included in the list of incremental changes to distinguish objects in the integrated circuit design database that were changed from the current state; and (g) streaming out the integrated circuit design database.

摘要翻译： 描述了用于验证集成电路设计的增量变化的方法和计算机程序产品，其包括以下步骤：（a）作为输入接收集成电路设计数据库; （b）接收工程变更单作为输入; （c）识别和标记集成电路设计数据库中的对象，以指示集成电路设计数据库的当前状态; （d）将工程变更单应用于集成电路设计数据库; （e）分析集成电路设计数据库，以生成由工程变更订单产生的对集成电路设计数据库的增量变化的列表; （f）识别和标记增量变化列表中集成电路设计数据库中的对象，以区分从当前状态改变的集成电路设计数据库中的对象; 和（g）流出集成电路设计数据库。

公开(公告)号：US20060064656A1

公开(公告)日：2006-03-23

申请号：US10947498

申请日：2004-09-22

申请人： Viswanathan Lakshmanan ,  Alan Holesovsky ,  Lisa Miller ,  Jonathan Kuppinger

发明人： Viswanathan Lakshmanan ,  Alan Holesovsky ,  Lisa Miller ,  Jonathan Kuppinger

IPC分类号： G06F17/50 ,  G06F9/45

CPC分类号： G06F17/5081

摘要： A method and computer program product for early physical design validation and identification of texted metal short circuits in an integrated circuit design includes steps of: (a) receiving as input a representation of an integrated circuit design; (b) receiving as input a physical design rule deck that specifies rule checks to be performed on the integrated circuit design; (c) generating a specific rule deck from the physical design rule deck wherein the specific rule deck includes only physical design rules that are specific to one of identifying texted metal short circuits in the integrated circuit design and power distribution and input/output cell placement in the integrated circuit design; and (d) performing a physical design validation on the integrated circuit design from the specific rule deck.

摘要翻译： 用于集成电路设计中的短信金属短路的早期物理设计验证和识别的方法和计算机程序产品包括以下步骤：（a）作为输入接收集成电路设计的表示; （b）作为输入接收指定要在集成电路设计上执行的规则检查的物理设计规则卡; （c）从物理设计规则甲板生成特定规则甲板，其中特定规则甲板仅包括专用于识别集成电路设计中的发短信的金属短路和电力分配以及输入/输出电池放置之一的物理设计规则 集成电路设计; 和（d）从特定的规则层面对集成电路设计进行物理设计验证。