Collapsible container
    11.
    发明申请
    Collapsible container 失效
    可折叠集装箱

    公开(公告)号:US20050061811A1

    公开(公告)日:2005-03-24

    申请号:US10671053

    申请日:2003-09-22

    Applicant: Hui-Min Wang

    Inventor: Hui-Min Wang

    CPC classification number: B65D5/3614 B65D2313/02

    Abstract: A collapsible container includes a rectangular bottom, a front and a rear rectangular wall pivotally turnably connected to a front and a rear edge, respectively, of the bottom along two folding lines, two rectangular side walls pivotally turnably connected to two lateral ends of each of the front and the rear wall along two folding lines, and two locating flaps pivotally turnably connected to two lateral edges of the bottom along two folding lines. Each of the two locating flaps is an isosceles triangle having two equal lateral sides separately corresponding to a diagonal of the sidewall. Moreover, fastening elements are correspondingly provided on an inner surface of each side wall and an outer surface of the locating flap to enable detachable connection of the side walls to the locating flaps and accordingly free collapse and extension of the container.

    Abstract translation: 可折叠容器包括矩形底部,前后矩形壁,其分别沿着两条折叠线可转动地连接到底部的前边缘和后边缘,两个矩形侧壁可转动地连接到每个的两个侧端 沿着两条折叠线的前壁和后壁,以及沿两条折叠线可枢转地可转动地连接到底部的两个侧边缘的两个定位翼片。 两个定位翼片中的​​每一个是等腰三角形,其具有分别对应于侧壁的对角线的两个相等的侧边。 此外,紧固元件相应地设置在每个侧壁的内表面和定位翼片的外表面上,以使得侧壁能够与定位翼片可拆卸地连接,并因此自由地使容器的塌缩和延伸。

    Audio clock regenerator with precisely tracking mechanism
    13.
    发明授权
    Audio clock regenerator with precisely tracking mechanism 有权
    音频时钟再生器具有精确的跟踪机制

    公开(公告)号:US08063986B2

    公开(公告)日:2011-11-22

    申请号:US11757829

    申请日:2007-06-04

    Applicant: Hui-Min Wang

    Inventor: Hui-Min Wang

    CPC classification number: H03L7/07 H03L7/235 H04N21/4305

    Abstract: In an HDMI system, the clock regenerator proposed by the HDMI specification may suffer external noise because the input clock of a phase lock loop circuit in a sink device of the HDMI system is too slow. This slow input clock causes the phase lock loop circuit unable to adjust and reduce the jitter of an audio clock regenerated in the sink device. Therefore, one embodiment of the present invention provides a clock regenerator to extract the relationship between the regenerated audio clock and a video clock received by the sink device from other source devices. The clock regenerator may comprise a phase lock loop circuit, a recovery circuit, a crystal oscillator and a tracking circuit. The crystal oscillator generates a crystal clock. The phase lock loop circuit receives the crystal clock and regenerates an audio clock. The recovery circuit extracts the relationship between the audio clock and the received video clock. The tracking circuit tunes the frequency of the crystal clock based on the extracted relationship.

    Abstract translation: 在HDMI系统中,HDMI规范提出的时钟再生器可能会受到外部噪声,因为HDMI系统的信宿设备中的锁相环电路的输入时钟太慢。 这种慢速输入时钟使得锁相环电路不能调节并减少在宿设备中再生的音频时钟的抖动。 因此,本发明的一个实施例提供了一种时钟再生器,用于提取再生的音频时钟与宿设备从其它源设备接收的视频时钟之间的关系。 时钟再生器可以包括锁相环电路,恢复电路,晶体振荡器和跟踪电路。 晶体振荡器产生晶体时钟。 锁相环电路接收晶体钟并重新生成音频时钟。 恢复电路提取音频时钟和接收的视频时钟之间的关系。 跟踪电路根据提取的关系调整晶体时钟的频率。

    Standby circuit and method for a display device
    14.
    发明授权
    Standby circuit and method for a display device 有权
    显示设备的待机电路和方法

    公开(公告)号:US08049696B2

    公开(公告)日:2011-11-01

    申请号:US12326855

    申请日:2008-12-02

    Applicant: Hui-Min Wang

    Inventor: Hui-Min Wang

    CPC classification number: G09G5/006 G09G2330/022 G09G2370/12

    Abstract: A standby circuit and method for a display device is disclosed. A detector detects voltage drop of the first termination resistor of a positive path of a clock channel, and the second termination resistors of a negative path. Upon detecting the voltage drop, a switch controller disconnects the positive path or the negative path that has the detected voltage drop, thereby saving power in the standby mode of the display device.

    Abstract translation: 公开了一种用于显示装置的备用电路和方法。 检测器检测时钟通道的正路径的第一终端电阻器的电压降和负路径的第二终端电阻器。 在检测到电压降时,开关控制器断开具有检测到的电压降的正路径或负路径,从而在显示装置的待机模式下节省功率。

    High frequency surface acoustic wave device and the substrate thereof
    16.
    发明授权
    High frequency surface acoustic wave device and the substrate thereof 有权
    高频声表面波装置及其基板

    公开(公告)号:US07741752B2

    公开(公告)日:2010-06-22

    申请号:US12232033

    申请日:2008-09-10

    CPC classification number: H03H3/10 H03H9/02574

    Abstract: A high frequency SAW device and the substrate thereof are disclosed. The disclosed high frequency SAW device does not need to use the conventional and expensive sapphire substrate as its substrate. Besides, the disclosed substrate for a high-frequency SAW device can replace the conventional sapphire substrate in the use of the substrate for a high frequency SAW device. The disclosed high frequency SAW device comprises: a substrate; a first buffering layer forming on the surface of the substrate; a second buffering layer forming on the surface of the first buffering layer; a piezoelectric layer forming on the surface of the second buffering layer; an input transformation unit; and an output transformation unit, wherein the input transformation unit and the output transformation unit are formed in pairs on the surface of or beneath the piezoelectric layer.

    Abstract translation: 公开了一种高频SAW器件及其基片。 所公开的高频SAW器件不需要使用常规和昂贵的蓝宝石衬底作为其衬底。 此外,所公开的用于高频SAW器件的衬底可以在使用用于高频SAW器件的衬底时替代传统的蓝宝石衬底。 所公开的高频SAW器件包括:衬底; 形成在所述基板的表面上的第一缓冲层; 形成在所述第一缓冲层的表面上的第二缓冲层; 形成在所述第二缓冲层的表面上的压电层; 输入变换单元; 以及输出变换单元,其中所述输入变换单元和所述输出变换单元成对地形成在所述压电层的表面上或下方。

    Standby Circuit and Method for a Display Device
    17.
    发明申请
    Standby Circuit and Method for a Display Device 有权
    待机电路和显示设备的方法

    公开(公告)号:US20100134391A1

    公开(公告)日:2010-06-03

    申请号:US12326855

    申请日:2008-12-02

    Applicant: Hui-Min Wang

    Inventor: Hui-Min Wang

    CPC classification number: G09G5/006 G09G2330/022 G09G2370/12

    Abstract: A standby circuit and method for a display device is disclosed. A detector detects voltage drop of the first termination resistor of a positive path of a clock channel, and the second termination resistors of a negative path. Upon detecting the voltage drop, a switch controller disconnects the positive path or the negative path that has the detected voltage drop, thereby saving power in the standby mode of the display device.

    Abstract translation: 公开了一种用于显示装置的备用电路和方法。 检测器检测时钟通道的正路径的第一终端电阻器的电压降和负路径的第二终端电阻器。 在检测到电压降时,开关控制器断开具有检测到的电压降的正路径或负路径,从而在显示装置的待机模式下节省功率。

    AUDIO CLOCK REGENERATOR WITH PRECISELY TRACKING MECHANISM
    18.
    发明申请
    AUDIO CLOCK REGENERATOR WITH PRECISELY TRACKING MECHANISM 有权
    具有精确跟踪机制的音频时钟再生器

    公开(公告)号:US20080298532A1

    公开(公告)日:2008-12-04

    申请号:US11757829

    申请日:2007-06-04

    Applicant: Hui-Min Wang

    Inventor: Hui-Min Wang

    CPC classification number: H03L7/07 H03L7/235 H04N21/4305

    Abstract: In an HDMI system, the clock regenerator proposed by the HDMI specification may suffer external noise because the input clock of a phase lock loop circuit in a sink device of the HDMI system is too slow. This slow input clock causes the phase lock loop circuit unable to adjust and reduce the jitter of an audio clock regenerated in the sink device. Therefore, one embodiment of the present invention provides a clock regenerator to extract the relationship between the regenerated audio clock and a video clock received by the sink device from other source devices. The clock regenerator may comprise a phase lock loop circuit, a recovery circuit, a crystal oscillator and a tracking circuit. The crystal oscillator generates a crystal clock. The phase lock loop circuit receives the crystal clock and regenerates an audio clock. The recovery circuit extracts the relationship between the audio clock and the received video clock. The tracking circuit tunes the frequency of the crystal clock based on the extracted relationship.

    Abstract translation: 在HDMI系统中,HDMI规范提出的时钟再生器可能会受到外部噪声,因为HDMI系统的信宿设备中的锁相环电路的输入时钟太慢。 这种慢速输入时钟使得锁相环电路不能调节并减少在宿设备中再生的音频时钟的抖动。 因此,本发明的一个实施例提供了一种时钟再生器,用于提取再生的音频时钟与宿设备从其它源设备接收的视频时钟之间的关系。 时钟再生器可以包括锁相环电路,恢复电路,晶体振荡器和跟踪电路。 晶体振荡器产生晶体时钟。 锁相环电路接收晶体钟并重新生成音频时钟。 恢复电路提取音频时钟和接收的视频时钟之间的关系。 跟踪电路根据提取的关系调整晶体时钟的频率。

    Reference voltage generator
    19.
    发明授权
    Reference voltage generator 有权
    参考电压发生器

    公开(公告)号:US07446599B1

    公开(公告)日:2008-11-04

    申请号:US11806107

    申请日:2007-05-30

    Applicant: Hui-Min Wang

    Inventor: Hui-Min Wang

    CPC classification number: G05F3/242

    Abstract: A reference voltage generator is provided. The reference voltage generator includes a bandgap reference circuit, a level shifter and a voltage divider. The bandgap reference circuit includes a current generator and a first BJT. The current generator outputs a reference current. The first BJT flows in the reference current from its emitter via a first resistor and has its collector and base grounded, such that a bandgap reference voltage and a first bias voltage can be output at the connection between the current generator and the first resistor and at the emitter of the first BJT. The level shifter is coupled to the bandgap reference circuit and outputs a second bias voltage higher than the first bias voltage and unequal to the bandgap reference voltage. The voltage divider is connected between the second bias voltage and the bandgap reference voltage and outputs a reference voltage therebetween.

    Abstract translation: 提供了参考电压发生器。 参考电压发生器包括带隙参考电路,电平转换器和分压器。 带隙参考电路包括电流发生器和第一BJT。 电流发生器输出参考电流。 第一BJT通过第一电阻器从发射极流过参考电流,并且其集电极和基极接地,使得能够在电流发生器和第一电阻器之间的连接处输出带隙参考电压和第一偏置电压,并且在 第一个BJT的发射器。 电平移位器耦合到带隙参考电路,并输出高于第一偏置电压的第二偏置电压,并且不等于带隙参考电压。 分压器连接在第二偏置电压和带隙参考电压之间,并在其间输出参考电压。

    Current mode interface receiver with process insensitive common mode current extraction and the method
    20.
    发明授权
    Current mode interface receiver with process insensitive common mode current extraction and the method 有权
    电流模式接口接收器具有过程不敏感共模电流提取和方法

    公开(公告)号:US07400174B1

    公开(公告)日:2008-07-15

    申请号:US11621918

    申请日:2007-01-10

    Applicant: Hui-Min Wang

    Inventor: Hui-Min Wang

    CPC classification number: H04L25/0294 H04L25/0282

    Abstract: A data communication system comprises a transmitter and a receiver. A plurality of current mode drivers at the transmitter are used to transmit clock and data signals to the receiver. A plurality of current mode sinks at the receiver are used to receive the transmitted clock and data signal. The present invention provides an improved current mode interface receiver with a process insensitive common mode current extraction circuit. The proposed common mode current extraction circuit will generate a current reference based on the received clock signal, so as to accurately interpret the received clock and data signals.

    Abstract translation: 数据通信系统包括发射机和接收机。 发射机处的多个电流模式驱动器用于将时钟和数据信号传输到接收机。 在接收机处的多个当前模式信宿用于接收传输的时钟和数据信号。 本发明提供一种具有过程不敏感共模电流提取电路的改进的电流模式接口接收器。 所提出的共模电流提取电路将基于所接收的时钟信号产生电流参考,以便准确地解释所接收的时钟和数据信号。

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