-
公开(公告)号：US08300753B2
公开(公告)日：2012-10-30
申请号：US12510160
申请日：2009-07-27
IPC分类号： H04L7/00
CPC分类号： H04L7/033 , H03L7/0891 , H03L7/091 , H03L7/113 , H04L7/0004
摘要： In one embodiment, a method includes accessing a reference clock having a reference clock frequency and reference clock phase; generating an output clock having an output clock phase and output clock frequency that is a function of an analog control voltage setting and a frequency gain curve; fixing the analog control voltage setting to a predetermined voltage; selecting one of the frequency gain curves within a predetermined frequency range of the reference clock frequency at the analog control voltage setting; adjusting the analog control voltage setting to adjust the output clock frequency to be within another predetermined frequency range of the reference clock frequency; and adjusting the output clock phase to be within a predetermined phase range of an input data phase of the input data stream.
摘要翻译： 在一个实施例中，一种方法包括访问具有参考时钟频率和参考时钟相位的参考时钟; 产生具有作为模拟控制电压设定和频率增益曲线的函数的输出时钟相位和输出时钟频率的输出时钟; 将模拟控制电压设置固定为预定电压; 在模拟控制电压设定下，在参考时钟频率的预定频率范围内选择一个频率增益曲线; 调整所述模拟控制电压设定以将所述输出时钟频率调整到所述参考时钟频率的另一预定频率范围内; 以及将输出时钟相位调整在输入数据流的输入数据相位的预定相位范围内。
-
公开(公告)号：US20100091925A1
公开(公告)日：2010-04-15
申请号：US12510160
申请日：2009-07-27
IPC分类号： H04L7/02
CPC分类号： H04L7/033 , H03L7/0891 , H03L7/091 , H03L7/113 , H04L7/0004
摘要： In one embodiment, a method includes accessing a reference clock having a reference clock frequency and reference clock phase; generating an output clock having an output clock phase and output clock frequency that is a function of an analog control voltage setting and a frequency gain curve; fixing the analog control voltage setting to a predetermined voltage; selecting one of the frequency gain curves within a predetermined frequency range of the reference clock frequency at the analog control voltage setting; adjusting the analog control voltage setting to adjust the output clock frequency to be within another predetermined frequency range of the reference clock frequency; and adjusting the output clock phase to be within a predetermined phase range of an input data phase of the input data stream.
摘要翻译： 在一个实施例中，一种方法包括访问具有参考时钟频率和参考时钟相位的参考时钟; 产生具有作为模拟控制电压设定和频率增益曲线的函数的输出时钟相位和输出时钟频率的输出时钟; 将模拟控制电压设置固定为预定电压; 在模拟控制电压设定下，在参考时钟频率的预定频率范围内选择一个频率增益曲线; 调整所述模拟控制电压设定以将所述输出时钟频率调整到所述参考时钟频率的另一预定频率范围内; 以及将输出时钟相位调整在输入数据流的输入数据相位的预定相位范围内。
-
13.发明授权公开(公告)号：US07405593B2
公开(公告)日：2008-07-29
申请号：US11265550
申请日：2005-11-01
IPC分类号： H03K19/094
CPC分类号： H04L25/0282 , H03K3/356191 , H03K3/35625 , H04L25/0272 , H04L25/0294 , Y10T83/2037 , Y10T83/204
摘要： Disclosed are on-chip global electrical signaling systems and methods employing differential current-mode sensing having reduced delay and energy dissipation compared to conventional inverter repeaters. The present inventions can be used for point-to-point connections as well as N-to-1 connections.
摘要翻译： 本发明公开了采用差分电流模式感测的片上全球电信令系统和方法，与传统的逆变器中继器相比具有降低的延迟和能量消耗。 本发明可以用于点到点连接以及N到1连接。
-
公开(公告)号：US08411782B2
公开(公告)日：2013-04-02
申请号：US12511917
申请日：2009-07-29
CPC分类号： H04L25/14
摘要： In one embodiment, a method includes receiving input data bits at a collective data rate, the input data bits being grouped into a plurality of input data words, the input data bits of each of the input data words being received from n parallel input-data-bit streams, each of the n parallel input-data-bit streams having a stream data rate that is 1/n of the collective data rate, each of the input data words comprising n consecutive ones of the input data bits; selecting particular input data bits; and generating a k-bit deskew channel with the selected input data bits, the deskew channel comprising a number of frames, each of the frames comprising x input data bits from one or more input data words and one or more framing bits. In another embodiment, a method includes using such a deskew channel to determine relative delays between data channels and the deskew channel.
摘要翻译： 在一个实施例中，一种方法包括以集体数据速率接收输入数据位，输入数据位被分组成多个输入数据字，每个输入数据字的输入数据位从n个并行输入数据 每个n个并行输入数据比特流具有作为集合数据速率的1 / n的流数据速率，每个输入数据字包括n个连续的输入数据位; 选择特定输入数据位; 以及生成具有所选择的输入数据位的k位去偏移通道，所述歪斜通道包括多个帧，每个帧包括来自一个或多个输入数据字的x个输入数据位和一个或多个成帧位。 在另一个实施例中，一种方法包括使用这种歪斜通道来确定数据通道和歪斜通道之间的相对延迟。
-
公开(公告)号：US20100086075A1
公开(公告)日：2010-04-08
申请号：US12511917
申请日：2009-07-29
IPC分类号： H04B7/02
CPC分类号： H04L25/14
摘要： In one embodiment, a method includes receiving input data bits at a collective data rate, the input data bits being grouped into a plurality of input data words, the input data bits of each of the input data words being received from n parallel input-data-bit streams, each of the n parallel input-data-bit streams having a stream data rate that is 1/n of the collective data rate, each of the input data words comprising n consecutive ones of the input data bits; selecting particular input data bits; and generating a k-bit deskew channel with the selected input data bits, the deskew channel comprising a number of frames, each of the frames comprising x input data bits from one or more input data words and one or more framing bits. In another embodiment, a method includes using such a deskew channel to determine relative delays between data channels and the deskew channel.
摘要翻译： 在一个实施例中，一种方法包括以集体数据速率接收输入数据位，输入数据位被分组成多个输入数据字，每个输入数据字的输入数据位从n个并行输入数据 每个n个并行输入数据比特流具有作为集合数据速率的1 / n的流数据速率，每个输入数据字包括n个连续的输入数据位; 选择特定输入数据位; 以及生成具有所选择的输入数据位的k位去偏移通道，所述歪斜通道包括多个帧，每个帧包括来自一个或多个输入数据字的x个输入数据位和一个或多个成帧位。 在另一个实施例中，一种方法包括使用这种歪斜通道来确定数据通道和歪斜通道之间的相对延迟。
-
16.发明授权Electronic oscillators having a plurality of phased outputs and such oscillators with phase-setting and phase-reversal capability 有权具有多个相控输出的电子振荡器和具有相位设定和相位反转能力的这种振荡器公开(公告)号：US07616070B2
公开(公告)日：2009-11-10
申请号：US11934998
申请日：2007-11-05
IPC分类号： H03B27/00
CPC分类号： H03K3/0315 , H03B27/00
摘要： Disclosed are multiphase oscillators comprising a plurality of delay stages serially coupled in a loop by a plurality of nodes, with the loop being folded to provide two concentric rings of delay stages with equal numbers of allocated nodes. A second plurality of negative-resistance elements are provided, each element having a first output coupled to a node on the first concentric ring and a second output coupled to a node on the second concentric ring. Each such output switches between first and second voltage levels, and provides a negative resistance to a signal coupled to it during at least a portion of the transition between voltage levels. The outputs of an element switch to opposite voltage levels. With this construction, a high-voltage pulse propagates around the loop of delay stages, with a low-voltage pulse propagating behind it. Also disclosed are circuits to control the direction of pulse propagation.
摘要翻译： 公开了多相振荡器，其包括多个延迟级，多个延迟级由多个节点在环路中串联耦合，环路被折叠以提供具有相等数量的分配节点的延迟级的两个同心环。 提供了第二多个负电阻元件，每个元件具有耦合到第一同心环上的节点的第一输出和耦合到第二同心环上的节点的第二输出。 每个这样的输出在第一和第二电压电平之间切换，并且在电压电平之间的至少一部分转换期间向与其耦合的信号提供负电阻。 元件的输出切换到相反的电压电平。 利用这种结构，高压脉冲在延迟级的环路周围传播，低压脉冲在其后面传播。 还公开了控制脉冲传播方向的电路。
-
公开(公告)号：US06842046B2
公开(公告)日：2005-01-11
申请号：US10066355
申请日：2002-01-31
IPC分类号： H03K19/0185 , H03K19/096
CPC分类号： H03K19/01855
摘要： A system and method, for converting a voltage input from a low voltage source to a voltage output at a high voltage source using a domino logic circuit design. An embodiment provides a low to high voltage conversion system. The system includes: a pull-up transistor coupled to a high voltage source for charging a node, when a precharge signal is received; a low voltage source used for setting an input voltage; a pull-down network for discharging the node depending, at least in part, on the input voltage; and an output voltage determined from the node.
摘要翻译： 一种用于使用多米诺逻辑电路设计将从低电压源输入的电压转换为高电压源的电压输出的系统和方法。 实施例提供了一种低至高电压转换系统。 该系统包括：当接收到预充电信号时，耦合到高电压源的上拉晶体管用于对节点充电; 用于设定输入电压的低电压源; 至少部分地基于所述输入电压的用于对所述节点进行放电的下拉网络; 和从该节点确定的输出电压。
-
18.发明授权Electronic oscillators having a plurality of phased outputs and such oscillators with phase-setting and phase-reversal capability 有权具有多个相控输出的电子振荡器和具有相位设定和相位反转能力的这种振荡器公开(公告)号：US07307483B2
公开(公告)日：2007-12-11
申请号：US11347460
申请日：2006-02-03
IPC分类号： H03B27/00
CPC分类号： H03K3/0315 , H03B27/00
摘要： Disclosed are multiphase oscillators comprising a plurality of delay stages serially coupled in a loop by a plurality of nodes, with the loop being folded to provide two concentric rings of delay stages with equal numbers of allocated nodes. A second plurality of negative-resistance elements are provided, each element having a first output coupled to a node on the first concentric ring and a second output coupled to a node on the second concentric ring. Each such output switches between first and second voltage levels, and provides a negative resistance to a signal coupled to it during at least a portion of the transition between voltage levels. The outputs of an element switch to opposite voltage levels. With this construction, a high-voltage pulse propagates around the loop of delay stages, with a low-voltage pulse propagating behind it. Also disclosed are circuits to control the direction of pulse propagation.
摘要翻译： 公开了多相振荡器，其包括多个延迟级，多个延迟级由多个节点在环路中串联耦合，环路被折叠以提供具有相等数量的分配节点的延迟级的两个同心环。 提供了第二多个负电阻元件，每个元件具有耦合到第一同心环上的节点的第一输出和耦合到第二同心环上的节点的第二输出。 每个这样的输出在第一和第二电压电平之间切换，并且在电压电平之间的至少一部分转换期间向与其耦合的信号提供负电阻。 元件的输出切换到相反的电压电平。 利用这种结构，高压脉冲在延迟级的环路周围传播，低压脉冲在其后面传播。 还公开了控制脉冲传播方向的电路。
-
公开(公告)号：US06693459B2
公开(公告)日：2004-02-17
申请号：US10045179
申请日：2002-01-11
IPC分类号： H03K19096
CPC分类号： H03K3/012 , H03K3/356139
摘要： The present invention provides techniques, including a system and method, for improving speed in a flip-flop, having a pre-charged stage coupled to an evaluation stage. In one exemplary embodiment delay is reduced by using a conditional rather than an unconditional keeper, where the conditional keeper has the function of a keeper only under certain conditions. In some embodiments there is a conditional keeper in either the pre-charged stage or the evaluation stage or both stages. Another embodiment provides for the combining of the evaluation stage with one or more external logic functions.
摘要翻译： 本发明提供了一种技术，包括用于提高触发器中的速度的系统和方法，其具有耦合到评估级的预充电级。 在一个示例性实施例中，通过使用条件而不是无条件守门员来减少延迟，其中条件保持者仅在某些条件下具有保持者的功能。 在一些实施例中，在预充电阶段或评估阶段或两个阶段中存在条件保持器。 另一个实施例提供了评估阶段与一个或多个外部逻辑功能的组合。
-
公开(公告)号：US20120023380A1
公开(公告)日：2012-01-26
申请号：US12840985
申请日：2010-07-21
申请人： Samir Parikh , Nikola Nedovic , William W. Walker
发明人： Samir Parikh , Nikola Nedovic , William W. Walker
IPC分类号： G06F11/07
CPC分类号： H04L25/14
摘要： In one embodiment, a method includes receiving input data bits over data channels; receiving deskew channel bits constituting frames that each comprise ones of the input data bits; determining frame boundaries; mapping each of the input data bits in each of the frames to one of the data channels; for each set of the frames, comparing the input data bits in the set with the input data bits in the corresponding input data words; determining relative delays among the data channels and the deskew channel; when non-zero delays are determined, rearranging the input data bits to reduce the delays; and when it is determined that one or more of the data channels have a delay of greater than a predetermined number of data-channel clock periods relative to a particular data channel, delaying input data bits in the particular data channel by an additional number of input data bits.
摘要翻译： 在一个实施例中，一种方法包括：通过数据信道接收输入数据位; 接收构成每个包括所述输入数据位中的一个的帧的歪斜通道位; 确定帧边界; 将每个帧中的每个输入数据位映射到数据信道之一; 对于每组帧，将该组中的输入数据位与相应输入数据字中的输入数据位进行比较; 确定数据通道和歪斜通道之间的相对延迟; 当确定非零延迟时，重新排列输入数据位以减少延迟; 并且当确定一个或多个数据信道相对于特定数据信道具有大于预定数量的数据信道时钟周期的延迟时，通过附加数量的输入来延迟特定数据信道中的输入数据位 数据位。
-
-
-
-
-
-
-
-
-
搜索结果
45 条记录 (耗时 0.025 秒)
