公开(公告)号：US20220254292A1

公开(公告)日：2022-08-11

申请号：US17644627

申请日：2021-12-16

Applicant: Xiamen Tianma Micro-Electronics Co., Ltd.

Inventor： Qingjun LAI ,  Yihua ZHU ,  Yong YUAN ,  Ping AN ,  Zhaokeng CAO

IPC: G09G3/20

Abstract: An inverter, a method for driving an inverter, a driving circuit and a display panel are provided. An inverter includes a first module; a second module; an initial signal input terminal; and a first level signal input terminal. The first module includes a first transistor, a second transistor, and a third transistor; control terminals of the first transistor and the second transistor are both electrically connected to the initial signal input terminal; a first terminal of the third transistor is electrically connected to the first level signal input terminal; a first terminal of the second transistor is electrically connected to a first terminal of the second transistor; a second terminal of the second transistor is electrically connected to a control terminal of the third transistor; the first module includes a leakage current control component at least electrically connected with the second terminal of the first transistor.

公开(公告)号：US20220208797A1

公开(公告)日：2022-06-30

申请号：US17452969

申请日：2021-10-29

Applicant: Xiamen Tianma Micro-Electronics Co., Ltd.

Inventor： Qingjun LAI ,  Yihua ZHU ,  Yong YUAN ,  Ping AN ,  Zhaokeng CAO

IPC: H01L27/12 ,  G09G3/3225

Abstract: A display panel and a display device are provided in the present disclosure. The display panel includes a base substrate, a first transistor, a second transistor, a pixel circuit, and a drive circuit. A first active layer of the first transistor includes silicon; and a second active layer of the second transistor includes an oxide semiconductor. A length of a channel region of the first transistor is LL a distance between a first gate electrode and the first active layer is D1, and a first area S1=L1×D1; and a length of a channel region of the second transistor is L2, a distance between a second gate electrode and the second active layer is D2, and a second area S2=L2×D2, where S1

公开(公告)号：US20220123082A1

公开(公告)日：2022-04-21

申请号：US17514547

申请日：2021-10-29

Applicant: Xiamen Tianma Micro-Electronics Co., Ltd.

Inventor： Shui HE ,  Ping AN

IPC: H01L27/32 ,  G09G3/3233

Abstract: Disclosed are a display panel and a display device. The display panel includes a base substrate, a first transistor, a second transistor, a first conductive layer and a second conductive layer. A second source of the second transistor is connected to a second active layer of the second transistor through the first conductive layer, a second drain is connected to the second active layer through the second conductive layer, and a second gate of the second transistor is overlapped with a channel region, the first conductive layer and the second conductive layer are located in a non-channel region, a width W1 of a first gap between the first conductive layer and the second gate is greater than 0, a width of a second gap W2 between the second conductive layer and the second gate is greater than 0.

公开(公告)号：US20230378198A1

公开(公告)日：2023-11-23

申请号：US18229082

申请日：2023-08-01

Applicant: Xiamen Tianma Micro-Electronics Co., Ltd.

Inventor： Shui HE ,  Ping AN ,  Yaqi KUANG

IPC: H01L27/12

CPC classification number: H01L27/1248 ,  H01L27/1225 ,  H01L27/1251

Abstract: Provided are a display panel and a display device. The display panel includes a base substrate; a first transistor, a second transistor and a third transistor, where the first transistor, the second transistor and the third transistor are formed on the base substrate, the first transistor includes a first active layer, a first gate, a first source, and a first drain, the first active layer contains silicon, the second transistor includes a second active layer, a second gate, a second source, and a second drain, and the second active layer contains an oxide semiconductor and is disposed on one side of the first active layer facing away from the base substrate; and a first insulating layer and a second insulating layer, where the first insulating layer is disposed on one side of the second active layer facing away from the base substrate and between the second gate and the second active layer.

公开(公告)号：US20230230539A1

公开(公告)日：2023-07-20

申请号：US18187707

申请日：2023-03-22

Applicant: Xiamen Tianma Micro-Electronics Co., Ltd.

Inventor： Jieliang LI ,  Ping AN

IPC: G09G3/3233 ,  H01L27/12

CPC classification number: G09G3/3233 ,  H01L27/124 ,  G09G2300/0819 ,  G09G2320/045 ,  G09G2310/08

Abstract: A display panel includes a pixel circuit and a light-emitting element. The pixel circuit includes a data write device, a drive device and a bias adjustment device. The pixel circuit further includes a reset device or an initialization device. The display panel further includes a bias adjustment signal line, the bias adjustment signal line is connected to the bias adjustment device and configured to provide a bias adjustment signal; and at least one of a reset signal line or an initialization signal line, the reset signal line is connected to the reset device and configured to provide a reset signal, or the initialization signal line is connected to the initialization device and configured to provide an initialization signal. At least one side frame of the display panel includes a bias adjustment signal bus, at least one of a reset signal bus or an initialization signal bus.

公开(公告)号：US20230222968A1

公开(公告)日：2023-07-13

申请号：US18187716

申请日：2023-03-22

Applicant: Xiamen Tianma Micro-Electronics Co., Ltd.

Inventor： Jieliang LI ,  Ping AN

IPC: G09G3/3233 ,  G09G3/32 ,  G09G3/3291

CPC classification number: G09G3/3233 ,  G09G3/32 ,  G09G3/3291 ,  G09G2310/08 ,  G09G2310/061 ,  G09G2320/0233

Abstract: A display panel includes a pixel circuit and a light-emitting element. The pixel circuit includes a data write device, a drive device and a bias adjustment device. The data write device is configured to provide a data signal to the drive device. The bias adjustment device is configured to provide a bias adjustment signal to the drive device. The display panel further includes a drive circuit, the drive circuit is configured to receive a first drive signal and a second drive signal. In a case where the drive device includes a drive transistor being a PMOS transistor, the bias adjustment signal is same as the first drive signal, or, in a case where the drive device includes a drive transistor being an NMOS transistor, and the bias adjustment signal is same as the second drive signal.

公开(公告)号：US20230222966A1

公开(公告)日：2023-07-13

申请号：US18187711

申请日：2023-03-22

Applicant: Xiamen Tianma Micro-Electronics Co., Ltd.

Inventor： Jieliang LI ,  Ping AN

IPC: G09G3/3233 ,  G09G3/32

CPC classification number: G09G3/3233 ,  G09G3/32 ,  G09G2310/061 ,  G09G2310/0216 ,  G09G2320/0233

Abstract: A display panel includes a pixel circuit and a light-emitting element. The pixel circuit includes a data write device, a drive device and a bias adjustment device. The display panel further includes a bias adjustment signal line, a reset signal line or an initialization signal line. At least one side frame of the display panel includes a bias adjustment signal bus, a reset signal bus or an initialization signal bus. The bias adjustment signal bus is disposed in a first side frame of the display panel, the reset signal bus or the initialization signal bus is disposed in a second side frame of the display panel; and the first side frame is adjacent to the second side frame, or is opposite to the second side frame, or, the bias adjustment signal bus is disposed in a same side frame with the reset signal bus or the initialization signal bus.

公开(公告)号：US20220254291A1

公开(公告)日：2022-08-11

申请号：US17643557

申请日：2021-12-09

Applicant: Xiamen Tianma Micro-Electronics Co., Ltd.

Inventor： Qingjun LAI ,  Yihua ZHU ,  Yong YUAN ,  Ping AN ,  Zhaokeng CAO

IPC: G09G3/20 ,  G11C19/28

Abstract: A display panel and a display device are provided. The display panel includes a driving circuit. The driving circuit includes N levels of shift registers cascaded with each other, where N 2. A shift register of the N levels of shift registers includes: a first control unit, configured to receive an input signal and control a signal of a first node in response to a first clock signal; a second control unit, configured to receive a first voltage signal and a second voltage signal, and control a signal of a second node in response to the signal of the first node, the first clock signal, and a second clock signal; and a third control unit, configured to receive the first voltage signal and the second voltage signal, and control an output signal in response to the signal of the second node and a signal of the third node.

公开(公告)号：US20210327924A1

公开(公告)日：2021-10-21

申请号：US17364771

申请日：2021-06-30

Applicant: Xiamen Tianma Micro-Electronics Co., Ltd.

Inventor： Shui HE ,  Ping AN ,  Yaqi KUANG

IPC: H01L27/12

Abstract: Provided are a display panel and a display device. The display panel includes a base substrate; a first transistor and a second transistor, where the first transistor and the second transistor are formed on the base substrate, the first transistor includes a first active layer, a first gate, a first source, and a first drain, the first active layer contains silicon, the second transistor includes a second active layer, a second gate, a second source, and a second drain, and the second active layer contains an oxide semiconductor and is disposed on one side of the first active layer facing away from the base substrate; and a first insulating layer and a second insulating layer, where the first insulating layer is disposed on one side of the second active layer facing away from the base substrate and between the second gate and the second active layer.

公开(公告)号：US20250107333A1

公开(公告)日：2025-03-27

申请号：US18975960

申请日：2024-12-10

Applicant: Xiamen Tianma Micro-Electronics Co., Ltd.

Inventor： Shui HE ,  Ping AN

IPC: H10K59/121 ,  H01L29/786 ,  H10K59/126 ,  H10K59/131

Abstract: A display panel includes a first transistor and a second transistor, disposed over the base substrate. The first transistor includes a first active layer containing silicon, and the second transistor includes a second active layer containing an oxide semiconductor material. A shielding layer is on a side of the first active layer facing away from the base substrate, and on a side of the second active layer facing away from the base substrate. Along a projection direction perpendicular to the base substrate, the shielding layer covers the second active layer. The second transistor is included in a pixel circuit. A first driving signal line is connected to at least one of a second source, a second drain, and a second gate of the second transistor. Along the projection direction perpendicular to the base substrate, the shielding layer overlaps at least a portion of the first driving signal line.