公开(公告)号：US09652570B1

公开(公告)日：2017-05-16

申请号：US14845100

申请日：2015-09-03

Applicant: Xilinx, Inc.

Inventor： Vinod K. Kathail ,  L. James Hwang ,  Sundararajarao Mohan ,  Jorge E. Carrillo ,  Hua Sun ,  Tom Shui ,  Yogesh L. Chobe

IPC: G06F17/50

CPC classification number: G06F17/505

Abstract: Implementing a system-on-chip (SOC) design specified as a high level programming language (HLL) application may include querying, using a computer, a platform description to determine an available interface of a platform for a target integrated circuit and generating, using the computer, hardware for a function of the HLL application marked for hardware acceleration and hardware coupling the marked function with the available interface of the platform. Implementing the SOC design may also include modifying, using the computer, the HLL application with program code configured to access the generated hardware for the marked function and building, using the computer, the hardware and the software of the SOC design.

公开(公告)号：US08775986B1

公开(公告)日：2014-07-08

申请号：US13776350

申请日：2013-02-25

Applicant: Xilinx, Inc.

Inventor： Sundararajarao Mohan ,  L. James Hwang

IPC: G06F17/50

CPC classification number: G06F17/5054 ,  G06F11/3624 ,  G06F2217/14

Abstract: A method is provided for synthesizing an HLL program. For one or more variables to observe and/or control in a function of the HLL program, a first code segment is added to the function in the HLL program. For each of the one or more variables a respective second code segment is also added to the HLL program. In response to encountering the first code segment during synthesis of the HLL program, a memory is instantiated in a synthesized design. In response to encountering the second code segment during synthesis of the HLL program, a respective interface circuit is instantiated in the synthesized design. Each interface circuit is configured to replicate a state of the corresponding variable in the memory during operation of the synthesized design. A table is generated that maps names of the one or more variables to respective memory addresses in the memory.

Abstract translation: 提供了一种用于合成HLL程序的方法。 对于一个或多个变量来观察和/或控制HLL程序的功能，第一代码段被添加到HLL程序中的功能。 对于一个或多个变量中的每一个，相应的第二代码段也被添加到HLL程序。 响应在HLL程序的合成期间遇到第一代码段，在合成设计中实例化存储器。 响应于在HLL程序的合成期间遇到第二代码段，在合成设计中实例化了相应的接口电路。 每个接口电路被配置为在合成设计的操作期间复制存储器中相应变量的状态。 生成一个表，将一个或多个变量的名称映射到存储器中的各个存储器地址。