公开(公告)号：US10755013B1

公开(公告)日：2020-08-25

申请号：US16189919

申请日：2018-11-13

申请人： Xilinx, Inc.

发明人： Zhenman Fang ,  James L. Hwang ,  Samuel A. Skalicky ,  Tom Shui ,  Michael Gill ,  Welson Sun ,  Alfred Huang ,  Jorge E. Carrillo ,  Chen Pan

IPC分类号： G06F30/34 ,  G06F8/41 ,  G06F30/327

摘要： Creating a high-level language (HLL) callable library for a hardware core can include automatically querying, using computer hardware, a metadata description of a core to determine a plurality of available ports of the core, automatically determining, using the computer hardware, an argument of a first function specified in a header file corresponding to the core, mapping, using the computer hardware, the argument to a first port of the plurality of available ports, and automatically generating and storing, using the computer hardware, an HLL library specifying a mapping of the argument to the first port of the core. The HLL library is configured for inclusion with a user application during compilation.

公开(公告)号：US09075624B2

公开(公告)日：2015-07-07

申请号：US13925501

申请日：2013-06-24

申请人： Xilinx, Inc.

发明人： Jorge E. Carrillo

IPC分类号： G06F9/45 ,  G06F17/50

CPC分类号： G06F8/41 ,  G06F17/5054 ,  G06F2217/86

摘要： A method is provided for compiling an HLL program. A command is input that indicates a set of HLL source files to be compiled and a set of functions in the HLL source files that are to be implemented on programmable circuitry of a programmable IC. For a source file including one of the set of functions, a respective netlist is generated from HLL code of each of the set of functions included therein. Interface code is also generated for communication with the netlist. HLL code of the set of functions in the HLL source file is replaced with the generated interface code. Each HLL source file is compiled to produce a respective object file. The object files are linked to generate a program executable on the programmable IC. A configuration data stream is generated that implements each generated netlist on the programmable IC.

摘要翻译： 提供了一种用于编译HLL程序的方法。 输入一个命令，指示要编译的一组HLL源文件和将在可编程IC的可编程电路上实现的HLL源文件中的一组功能。 对于包括一组功能的源文件，从其中包括的功能集合中的每一个的HLL代码生成相应的网表。 也生成与网表进行通信的接口代码。 HLL源文件中的一组函数的HLL代码被替换为生成的接口代码。 每个HLL源文件被编译以产生相应的目标文件。 链接目标文件以生成可编程IC上可执行的程序。 生成在可编程IC上实现每个生成的网表的配置数据流。

公开(公告)号：US20140380287A1

公开(公告)日：2014-12-25

申请号：US13925501

申请日：2013-06-24

申请人： XILINX, INC.

发明人： Jorge E. Carrillo

IPC分类号： G06F9/45

CPC分类号： G06F8/41 ,  G06F17/5054 ,  G06F2217/86

摘要： A method is provided for compiling an HLL program. A command is input that indicates a set of HLL source files to be compiled and a set of functions in the HLL source files that are to be implemented on programmable circuitry of a programmable IC. For a source file including one of the set of functions, a respective netlist is generated from HLL code of each of the set of functions included therein. Interface code is also generated for communication with the netlist. HLL code of the set of functions in the HLL source file is replaced with the generated interface code. Each HLL source file is compiled to produce a respective object file. The object files are linked to generate a program executable on the programmable IC. A configuration data stream is generated that implements each generated netlist on the programmable IC.

摘要翻译： 提供了一种用于编译HLL程序的方法。 输入一个命令，指示要编译的一组HLL源文件和将在可编程IC的可编程电路上实现的HLL源文件中的一组功能。 对于包括一组功能的源文件，从其中包括的功能集合中的每一个的HLL代码生成相应的网表。 也生成与网表进行通信的接口代码。 HLL源文件中的一组函数的HLL代码被替换为生成的接口代码。 每个HLL源文件被编译以产生相应的目标文件。 链接目标文件以生成可编程IC上可执行的程序。 生成在可编程IC上实现每个生成的网表的配置数据流。

公开(公告)号：US09880966B1

公开(公告)日：2018-01-30

申请号：US14845127

申请日：2015-09-03

申请人： Xilinx, Inc.

发明人： L. James Hwang ,  Vinod K. Kathail ,  Sundararajarao Mohan ,  Jorge E. Carrillo ,  Hua Sun

IPC分类号： G06F13/24 ,  G06F13/40 ,  G06F13/42 ,  G06F3/00

CPC分类号： G06F13/4256 ,  G06F13/24 ,  G06F13/4022

摘要： Application-specific tailoring and reuse of a platform for a target integrated circuit may include determining, using a processor, a plurality of unused interfaces of the platform and determining, using the processor, connectivity of a circuit block to be coupled to the platform within the target integrated circuit. The method may include coupling, using the processor, the circuit block to the platform using an interface that is compatible with the circuit block and selected from the plurality of unused interfaces of the platform.

公开(公告)号：US09223921B1

公开(公告)日：2015-12-29

申请号：US14540854

申请日：2014-11-13

申请人： Xilinx, Inc.

发明人： Jorge E. Carrillo ,  L. James Hwang ,  Hua Sun ,  Sundararajarao Mohan ,  Vinod K. Kathail

IPC分类号： G06F17/50

CPC分类号： G06F17/5054 ,  G06F8/447

摘要： In an example implementation, a method is provided for compiling an HLL source file. The HLL source file checked for function calls to a set of hardware-accelerated functions having hardware implementations specified in a hardware library. For each HLL function call to a hardware-accelerated function, a circuit design is retrieved from the hardware library. The circuit design specifies a hardware implementation of the hardware-accelerated function. HLL interface code configured to communicate with the hardware implementation of the hardware-accelerated function is also generated. The HLL function call to the hardware-accelerated function in the HLL source file is replaced with the generated interface code. The HLL source file is compiled to generate a program executable on a processor of a programmable IC. Configuration data is generated that implements the retrieved circuit designs on the programmable circuitry of the programmable IC.

摘要翻译： 在一个示例实现中，提供了一种用于编译HLL源文件的方法。 HLL源文件检查了对硬件库中指定的硬件实现的一组硬件加速功能的函数调用。 对于硬件加速功能的每个HLL函数调用，从硬件库检索电路设计。 电路设计规定了硬件加速功能的硬件实现。 HLL接口代码配置为与硬件通信实现硬件加速功能也被生成。 HLL源文件中的硬件加速功能的HLL函数调用将替换为生成的接口代码。 HLL源文件被编译成在可编程IC的处理器上生成可执行的程序。 生成配置数据，其实现在可编程IC的可编程电路上检索的电路设计。

公开(公告)号：US10977018B1

公开(公告)日：2021-04-13

申请号：US16704890

申请日：2019-12-05

申请人： Xilinx, Inc.

发明人： L. James Hwang ,  Michael Gill ,  Tom Shui ,  Jorge E. Carrillo ,  Alfred Huang ,  Sudipto Chakraborty

IPC分类号： G06F9/44 ,  G06F8/41 ,  G06F8/30

摘要： Implementing an application within a heterogeneous device can include receiving an application specifying a plurality of hardware accelerators and having a plurality of sections corresponding to different subsystems of the heterogeneous device, wherein the plurality of sections are specified using different programming models. Compiling each section based on the programming model of the section and the subsystem of the heterogeneous device corresponding to the section into an accelerator representation. Linking the accelerator representations based on a platform of the heterogeneous device, generating a hardware implementation of the application for the heterogeneous device based on the linked accelerator implementations, and automatically generating program code configured to control one or more of the plurality of hardware accelerators of the hardware implementation.

公开(公告)号：US09805152B1

公开(公告)日：2017-10-31

申请号：US15046147

申请日：2016-02-17

申请人： Xilinx, Inc.

发明人： Jorge E. Carrillo ,  Vinod K. Kathail ,  L. James Hwang ,  Sundararajarao Mohan ,  Hua Sun

IPC分类号： G06F17/50

CPC分类号： G06F17/505

摘要： In an example implementation, a method is provided for compiling an HLL source file including function calls to one or more hardware accelerated functions. Function calls in the HLL source file to hardware accelerated functions are identified and grouped into a plurality of subsets for exclusive implementation in programmable logic resources. Sets of configuration data are generated for configuration of the programmable logic resources to implement hardware accelerated functions for the respective subsets of function calls. An interface manager is generated and the identified function calls are replaced with interface code configured to communicate with the interface manager. The interface manager manages configuration of the programmable logic resources to switch between the sets of configuration data to implement hardware accelerated functions for different ones of the subsets.

公开(公告)号：US09652570B1

公开(公告)日：2017-05-16

申请号：US14845100

申请日：2015-09-03

申请人： Xilinx, Inc.

发明人： Vinod K. Kathail ,  L. James Hwang ,  Sundararajarao Mohan ,  Jorge E. Carrillo ,  Hua Sun ,  Tom Shui ,  Yogesh L. Chobe

IPC分类号： G06F17/50

CPC分类号： G06F17/505

摘要： Implementing a system-on-chip (SOC) design specified as a high level programming language (HLL) application may include querying, using a computer, a platform description to determine an available interface of a platform for a target integrated circuit and generating, using the computer, hardware for a function of the HLL application marked for hardware acceleration and hardware coupling the marked function with the available interface of the platform. Implementing the SOC design may also include modifying, using the computer, the HLL application with program code configured to access the generated hardware for the marked function and building, using the computer, the hardware and the software of the SOC design.