公开(公告)号：US09483597B1

公开(公告)日：2016-11-01

申请号：US14667324

申请日：2015-03-24

Applicant: Xilinx, Inc.

Inventor： Sabyasachi Das ,  Ruibing Lu ,  Zhiyong Wang

IPC: G06F17/50

CPC classification number: G06F17/5068 ,  G06F17/5031 ,  G06F17/5072 ,  G06F17/5077 ,  G06F2217/84

Abstract: In an example, a method of implementing a circuit design for an integrated circuit (IC) includes: placing and routing a logical description of the circuit design to generate a physical description having a plurality of paths, and executing a timing analysis to determine a timing profile of the physical description. The method further includes optimizing the physical description by performing a plurality of iterations of: comparing the timing profile with a timing constraint to select a candidate set of paths having negative slack from the plurality of paths in the physical description; and modifying the physical description based on at least one optimization of a selected path from the candidate set of paths having a most negative slack. The method further includes generating a physical implementation of the circuit design for the IC based on the physical description.

Abstract translation: 在一个示例中，实现集成电路（IC）的电路设计的方法包括：放置和布线电路设计的逻辑描述以产生具有多个路径的物理描述，并且执行定时分析以确定时序 档案的物理描述。 该方法还包括通过执行多个迭代来优化物理描述：将定时简档与定时约束进行比较，以在物理描述中选择具有来自多个路径的负松弛的候选路径集合; 以及基于来自具有最负的松弛的路径的候选组的所选路径的至少一个优化来修改所述物理描述。 该方法还包括基于物理描述生成用于IC的电路设计的物理实现。