中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

11 records (took 0.018 seconds)

    Physical synthesis within placement
    1.
    发明授权
    Physical synthesis within placement 有权

    公开(公告)号：US10572621B1

    公开(公告)日：2020-02-25

    申请号：US16034242

    申请日：2018-07-12

    Applicant: Xilinx, Inc.

    Inventor： Zhiyong Wang ,  Sabyasachi Das

    IPC: G06F17/50

    Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for performing physical synthesis with an overall placement process. One of the methods includes receiving an initial netlist of a circuit design for an IC. A global placement process is performed that assigns to some components in the initial netlist a respective initial location on the IC. One or more physical synthesis processes are performed to generate a modified netlist before assigning a final location to all components in the circuit design by an overall placement process. A subsequent placement process is performed to assign a final location on the IC to all components in the modified netlist.

    Selective addition of clock buffers to a circuit design
    3.
    发明授权
    Selective addition of clock buffers to a circuit design 有权
    选择性地添加时钟缓冲器到电路设计

    公开(公告)号：US09235660B1

    公开(公告)日：2016-01-12

    申请号：US14243506

    申请日：2014-04-02

    Applicant: Xilinx, Inc.

    Inventor： Ruibing Lu ,  Sabyasachi Das ,  Zhiyong Wang

    IPC: G06F17/50

    CPC classification number: G06F17/50 ,  G06F17/505 ,  G06F2217/62

    Abstract: In an approach for processing a circuit design by a programmed processor, a placed circuit design that has been placed on programmable resources of a programmable integrated circuit (IC) is input. A critical path is determined from a first sequential element to a second sequential element assigned to the placed circuit design. A first clock buffer that provides a clock signal to the first and second sequential elements is determined, and an unused clock buffer is selected based on proximity to the first sequential element. The circuit design is modified to include the unused clock buffer as a second clock buffer coupled to receive a clock signal in parallel with the first clock buffer and to provide a clock signal to the first sequential element.

    Abstract translation: 在通过编程处理器处理电路设计的方法中，输入放置在可编程集成电路（IC）的可编程资源上的放置电路设计。 从第一顺序元件确定关键路径到分配给放置的电路设计的第二顺序元件。 确定向第一和第二顺序元件提供时钟信号的第一时钟缓冲器，并且基于与第一顺序元件的接近度来选择未使用的时钟缓冲器。 电路设计被修改为将未使用的时钟缓冲器包括为第二时钟缓冲器，其耦合以接收与第一时钟缓冲器并行的时钟信号，并向第一顺序元件提供时钟信号。

    Post-placement and pre-routing processing of critical paths in a circuit design
    4.
    发明授权
    Post-placement and pre-routing processing of critical paths in a circuit design 有权

    公开(公告)号：US09773083B1

    公开(公告)日：2017-09-26

    申请号：US15069598

    申请日：2016-03-14

    Applicant: Xilinx, Inc.

    Inventor： Sabyasachi Das ,  Zhiyong Wang

    IPC: G06F17/50

    CPC classification number: G06F17/5077 ,  G06F17/5072 ,  G06F2217/84

    Abstract: Aspects of processing a circuit design include synthesizing the circuit design and placing elements of the synthesized circuit design. After placing and before routing, respective delay values and slacks are determined. A first path having a most negative slack is determined and a first group of candidate paths is selected. The first group of candidate paths is a subset of critical paths of the circuit design, and the first group of candidate paths have delay values within a threshold range of delay values from the delay value of the first path. The first group of candidate paths are modified to reduce the respective delay values and a second group of candidate paths is selected. The second group of candidate paths have circuit structures that match selected circuit structures and are modified to reduce the respective delay values. A critical path having a most negative slack is iteratively selected and modified to reduce the respective delay value.

    Interactive multi-step physical synthesis
    5.
    发明授权
    Interactive multi-step physical synthesis 有权

    公开(公告)号：US09613173B1

    公开(公告)日：2017-04-04

    申请号：US14873072

    申请日：2015-10-01

    Applicant: Xilinx, Inc.

    Inventor： Rajat Aggarwal ,  Zhiyong Wang ,  Ruibing Lu ,  Sabyasachi Das

    IPC: G06F17/50

    CPC classification number: G06F17/5054 ,  G06F17/5072 ,  G06F17/5077 ,  G06F17/5081 ,  G06F2217/78 ,  G06F2217/84

    Abstract: A processor-implemented method is provided for placing and routing a circuit design. A first netlist is generated for the circuit design. Placement is performed for the first netlist on a target programmable integrated circuit (IC) to produce a first placed design. A set of optimizations are performed on the first placed design. The set of optimizations are recorded in an optimization history file. One or more optimizations specified in the optimization history file are performed on the first netlist to produce a second netlist that is different than the first netlist. Placement is performed for the second netlist on the target programmable IC to produce a second placed design that is different than the first placed design. Nets of the second placed design are routed to produce a placed and routed circuit design.

    Timing optimization of memory blocks in a programmable IC
    6.
    发明授权
    Timing optimization of memory blocks in a programmable IC 有权

    公开(公告)号：US10699053B1

    公开(公告)日：2020-06-30

    申请号：US15873724

    申请日：2018-01-17

    Applicant: Xilinx, Inc.

    Inventor： Zhiyong Wang ,  Ruibing Lu ,  Lin Chai ,  Sabyasachi Das

    IPC: G06F30/398 ,  G06F30/34 ,  G06F30/392 ,  G06F30/394 ,  G06F30/3312 ,  G06F30/39 ,  G06F30/327 ,  G06F119/12

    Abstract: Methods and apparatus for implementing a circuit design are provided. A physical description is generated corresponding to a predefined physical layout of a programmable integrated circuit. The circuit design includes a memory block. A timing analysis is executed to determine a first timing profile of the physical description. The physical description is optimized (or at least altered), and a physical implementation is generated based on the optimized physical description. Optimizing the physical description includes: selectively moving from or into the memory block of the physical description a register in response to an attribute of the memory block; executing a timing analysis to determine a second timing profile of the physical description with the register moved from or into the memory block of the physical description; comparing the first and second timing profiles; and selectively accepting or reversing the moving based on the comparison of the first and second timing profiles.

    Physical optimization for timing closure for an integrated circuit
    7.
    发明授权
    Physical optimization for timing closure for an integrated circuit 有权
    用于集成电路的时序闭合的物理优化

    公开(公告)号：US08984462B1

    公开(公告)日：2015-03-17

    申请号：US14249601

    申请日：2014-04-10

    Applicant: Xilinx, Inc.

    Inventor： Sabyasachi Das ,  Ruibing Lu ,  Zhiyong Wang ,  Aman Gayasen

    IPC: G06F17/50

    CPC classification number: G06F17/5054 ,  G06F2217/84

    Abstract: Physical optimization for timing closure for an integrated circuit includes processing a circuit design at least partially through a design flow to a late stage of the design flow. Using a processor, a baseline delay is calculated for each of a plurality of paths of the circuit design. A slack for each of the plurality of paths is determined. Physical optimization further includes selecting a path of the circuit design that meets a selection criterion according, at least in part, to the slack of the path, applying, using the processor, a physical optimization to the selected path resulting in an optimized path, and calculating a delay of the optimized path. The optimized path is incorporated into the circuit design only responsive to determining that the delay of the optimized path is less than the baseline delay of the selected path.

    Abstract translation: 用于集成电路的时序闭合的物理优化包括至少部分地通过设计流处理电路设计到设计流程的后期阶段。 使用处理器，为电路设计的多个路径中的每一个计算基线延迟。 确定多个路径中的每一个的松弛。 物理优化进一步包括至少部分地根据路径的松弛来选择满足选择标准的电路设计的路径，使用处理器对所选择的路径应用物理优化，得到优化的路径，以及 计算优化路径的延迟。 优化的路径被合并到电路设计中，仅响应于确定优化路径的延迟小于所选路径的基线延迟。

    INTERACTIVE MULTI-STEP PHYSICAL SYNTHESIS
    10.
    发明申请
    INTERACTIVE MULTI-STEP PHYSICAL SYNTHESIS 有权

    公开(公告)号：US20170098024A1

    公开(公告)日：2017-04-06

    申请号：US14873072

    申请日：2015-10-01

    Applicant: Xilinx, Inc.

    Inventor： Rajat Aggarwal ,  Zhiyong Wang ,  Ruibing Lu ,  Sabyasachi Das

    IPC: G06F17/50

    CPC classification number: G06F17/5054 ,  G06F17/5072 ,  G06F17/5077 ,  G06F17/5081 ,  G06F2217/78 ,  G06F2217/84

    Abstract: A processor-implemented method is provided for placing and routing a circuit design. A first netlist is generated for the circuit design. Placement is performed for the first netlist on a target programmable integrated circuit (IC) to produce a first placed design. A set of optimizations are performed on the first placed design. The set of optimizations are recorded in an optimization history file. One or more optimizations specified in the optimization history file are performed on the first netlist to produce a second netlist that is different than the first netlist. Placement is performed for the second netlist on the target programmable IC to produce a second placed design that is different than the first placed design. Nets of the second placed design are routed to produce a placed and routed circuit design.

Patent Agency Ranking