公开(公告)号：US20120158347A1

公开(公告)日：2012-06-21

申请号：US13324567

申请日：2011-12-13

申请人： Hiromasa NODA ,  Toshio Ninomiya

发明人： Hiromasa NODA ,  Toshio Ninomiya

IPC分类号： G06F19/00

CPC分类号： G11C29/028 ,  G11C29/021 ,  G11C29/023

摘要： A device includes a decoder, a selector, and a plurality of registers. The decoder is configured to generate a plurality of test signals. The selector is coupled to the decoder. The selector is configured to sequentially select a test signal from the plurality of test signals and to sequentially output the test signal selected. The plurality of registers is coupled in series to each other. The plurality of registers includes a first stage register. The first stage register is coupled to the selector to sequentially receive the test signal from the selector.

摘要翻译： 一种装置包括解码器，选择器和多个寄存器。 解码器被配置为产生多个测试信号。 选择器耦合到解码器。 选择器被配置为从多个测试信号中顺序地选择测试信号，并且顺序地输出所选择的测试信号。 多个寄存器彼此串联耦合。 多个寄存器包括第一级寄存器。 第一级寄存器耦合到选择器以顺序地从选择器接收测试信号。

公开(公告)号：US20090268542A1

公开(公告)日：2009-10-29

申请号：US12500023

申请日：2009-07-09

申请人： Hiromasa NODA

发明人： Hiromasa NODA

IPC分类号： G11C5/14 ,  G11C8/00

CPC分类号： G11C29/02 ,  G11C7/1045 ,  G11C11/4074 ,  G11C11/408 ,  G11C29/022 ,  G11C29/028 ,  G11C29/50008 ,  G11C2207/2227

摘要： A semiconductor memory device includes a row control circuit block and a column control circuit block each performing an access control over a memory cell array, a data I/O circuit block transmitting and receiving data to and from the memory cell array, and a control circuit changing at least a part of the row control circuit block, the column control circuit block, and the data I/O circuit block from a standby state into an active state in response to a setting of a predetermined mode signal to a mode register. According to the present invention, even if it is necessary to turn predetermined circuit blocks into the active state by an operation other than a read or write operation, there is no need to always set these circuit blocks into the active state.

摘要翻译： 半导体存储器件包括行控制电路块和列控制电路块，每个行控制电路块执行存储单元阵列上的访问控制，数据I / O电路块向存储单元阵列发送数据和从存储单元阵列接收数据;以及控制电路 响应于将预定模式信号设置到模式寄存器，将行控制电路块，列控制电路块和数据I / O电路块的至少一部分改变为从待机状态变为有效状态。 根据本发明，即使需要通过除了读取或写入操作之外的操作将预定的电路块转变为活动状态，也不需要总是将这些电路块设置为活动状态。