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公开(公告)号：US20240303209A1
公开(公告)日：2024-09-12
申请号：US18665365
申请日：2024-05-15
申请人： Uniquify, Inc.
发明人： Jung Lee , Venkat Iyer , Brett Murdock
IPC分类号： G06F13/362 , G06F13/16 , G06F13/42 , G11C8/18 , G11C29/02 , H03K5/00 , H03K5/133 , H03K5/14 , H03L7/08 , H03L7/081 , H03L7/10
CPC分类号： G06F13/3625 , G06F13/1689 , G06F13/4256 , G11C8/18 , G11C29/022 , G11C29/023 , G11C29/028 , H03K5/133 , H03K5/14 , H03L7/08 , H03L7/0812 , H03L7/10 , H03K2005/00019
摘要： A method for operating a data interface circuit whereby calibration adjustments for data bit capture are made without disturbing normal system operation includes initially establishing, using a first calibration method where a data bit pattern received by the data interface circuit is predictable, an optimal sampling point for sampling data bits received by the data interface circuit, and during a normal system operation and without disturbing the normal system operation, performing a second calibration method where the data bit pattern received by the data interface circuit is unpredictable. The second calibration method determines an amount of a timing drift for received data bit edge transitions and adjusts the optimal timing point determined by the first calibration method to create a revised optimal timing point. The second calibration method samples fringe timing points associated with the transition edges of a data bit.
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公开(公告)号：US12068050B2
公开(公告)日：2024-08-20
申请号：US17831329
申请日：2022-06-02
CPC分类号： G11C29/52 , G11C29/021 , G11C29/023
摘要： A method can include detecting, by a glitch detector coupled via a connection matrix to a first processing unit, an indication of a glitch on a memory system. The method can include notifying, via the connection matrix, at least a second processing unit of the detected indication of the glitch. The method can include subsequent to notifying at least the second processing unit, transmitting via the at least the second processing unit a glitch confirmation signal.
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公开(公告)号：US12047082B2
公开(公告)日：2024-07-23
申请号：US17994296
申请日：2022-11-26
发明人： Anil Kavala , Seonkyoo Lee , Taesung Lee , Jeongdon Ihm , Byunghoon Jeong
CPC分类号： H03L7/0816 , G11C7/222 , H03K5/133 , H03L7/085 , G11C29/023 , G11C29/028
摘要： A semiconductor device includes an internal clock generation circuit configured to generate an internal clock; a plurality of unit circuits configured to have a first unit circuit and a second unit circuit operating while being synchronized with an internal clock; a plurality of transfer circuits including a first transfer circuit configured to provide a first transfer path having a first delay time, and a second transfer circuit configured to provide a second transfer path having a second delay time different from the first delay time; and a delay compensation circuit configured to compare a first clock input to the first unit circuit through the first transfer path with a second clock input to the second unit circuit through the second transfer path, and to adjust the second delay time so that the adjusted second delay time matches the first delay time.
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公开(公告)号：US12019570B2
公开(公告)日：2024-06-25
申请号：US18149817
申请日：2023-01-04
发明人： Kang-Yong Kim , Dean Gans
CPC分类号： G06F13/1689 , G06F9/30145 , G11C7/222 , G11C29/023 , G11C29/028
摘要： Apparatuses and methods including memory commands for semiconductor memories are described. A controller provides a memory system with memory commands to access memory. The commands are decoded to provide internal signals and commands for performing operations, such as operations to access the memory array. The memory commands provided for accessing memory may include timing command and access commands. Examples of access commands include a read command and a write command. Timing commands may be used to control the timing of various operations, for example, for a corresponding access command. The timing commands may include opcodes that set various modes of operation during an associated access operation for an access command.
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公开(公告)号：US12001368B2
公开(公告)日：2024-06-04
申请号：US16752551
申请日：2020-01-24
发明人： Hyun Yoo Lee
CPC分类号： G06F13/4086 , G06F13/00 , G11C29/022 , G11C29/023 , G11C29/028 , G11C29/50008 , H04L25/0278 , H05K1/0246 , H05K1/025 , G11C2207/2254
摘要： Methods, systems, and apparatuses related to memory operation with common clock signals are provided. A memory device or system that includes one or more memory devices may be operable with a common clock signal without a delay from switching on-die termination on or off. For example, a memory device may comprise first impedance adjustment circuitry configured to provide a first impedance to a received clock signal having a clock impedance and second impedance adjustment circuitry configured to provide a second impedance to the received clock signal. The first impedance and the second impedance may be configured to provide a combined impedance about equal to the clock impedance when the first impedance adjustment circuitry and the second impedance adjustment circuitry are connected to the received clock signal in parallel.
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公开(公告)号：US11978498B2
公开(公告)日：2024-05-07
申请号：US17805989
申请日：2022-06-08
IPC分类号： H03K5/05 , G11C11/4076 , G11C29/02
CPC分类号： G11C11/4076 , G11C29/023 , H03K5/05
摘要： A method and an apparatus for testing an adjustment circuit is applied to a test platform. The adjustment circuit includes a duty cycle adjuster (DCA) circuit. The method includes: receiving written data at a specified storage address based on a first read/write clock signal; and receiving read data from the specified storage address based on a second read/write clock signal, and generating a test result of the DCA circuit based on the written data and the read data; wherein the DCA circuit is configured to adjust a first initial read/write clock signal to generate the first read/write clock signal and/or adjust a second initial read/write clock signal to generate the second read/write clock signal, and a duty cycle of the first initial read/write clock signal and/or a duty cycle of the second initial read/write clock signal have/has a first deviation.
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公开(公告)号：US11960418B2
公开(公告)日：2024-04-16
申请号：US17965684
申请日：2022-10-13
申请人： Rambus Inc.
IPC分类号： G11C7/10 , G06F13/16 , G06F13/40 , G11C5/02 , G11C7/22 , G11C8/18 , G11C11/4076 , G11C11/4093 , G11C11/4096 , G11C11/419 , G11C29/02
CPC分类号： G06F13/1673 , G06F13/4068 , G11C5/02 , G11C7/10 , G11C7/1012 , G11C7/1021 , G11C7/106 , G11C7/1066 , G11C7/1072 , G11C7/1087 , G11C7/1093 , G11C7/222 , G11C8/18 , G11C11/4076 , G11C11/4093 , G11C11/4096 , G11C11/419 , G11C29/022 , G11C29/023 , G11C29/028
摘要： A semiconductor memory system includes a first semiconductor memory die and a second semiconductor memory die. The first semiconductor memory die includes a primary data interface to receive an input data stream during write operations and to deserialize the input data stream into a first plurality of data streams, and also includes a secondary data interface, coupled to the primary data interface, to transmit the first plurality of data streams. The second semiconductor memory die includes a secondary data interface, coupled to the secondary data interface of the first semiconductor memory die, to receive the first plurality of data streams.
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公开(公告)号：US20240118837A1
公开(公告)日：2024-04-11
申请号：US18487955
申请日：2023-10-16
申请人： Rambus Inc.
CPC分类号： G06F3/0659 , G06F3/0604 , G06F3/0619 , G06F3/0638 , G06F3/0673 , G06F11/1076 , G11C7/1006 , G11C7/1009 , G11C7/1087 , G11C7/109 , G11C7/1093 , G11C29/023 , G11C29/028 , G11C2029/0411 , G11C2207/107
摘要： An memory component includes a memory bank and a command interface to receive a read-modify-write command, having an associated read address indicating a location in the memory bank and to either access read data from the location in the memory bank indicated by the read address after an adjustable delay period transpires from a time at which the read-modify-write command was received or to overlap multiple read-modify-write commands. The memory component further includes a data interface to receive write data associated with the read-modify-write command and an error correction circuit to merge the received write data with the read data to form a merged data and write the merged data to the location in the memory bank indicated by the read address.
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公开(公告)号：US20230410880A1
公开(公告)日：2023-12-21
申请号：US18209976
申请日：2023-06-14
申请人： Rambus Inc.
发明人： Thomas J. Giovannini , Alok Gupta , Ian Shaeffer , Steven C. Woo
IPC分类号： G11C11/4076 , G06F3/06 , G06F5/06 , G06F1/08 , G11C7/10 , G11C29/02 , G06F13/16 , G06F12/06 , G11C11/409
CPC分类号： G11C11/4076 , G06F3/0629 , G06F5/06 , G06F1/08 , G11C7/1087 , G11C7/1093 , G11C29/023 , G11C29/028 , G11C7/1078 , G06F13/1689 , G06F3/0634 , G06F12/0646 , G11C11/409 , G11C2207/2254 , G11C11/4096
摘要： A system that calibrates timing relationships between signals involved in performing write operations is described. This system includes a memory controller which is coupled to a set of memory chips, wherein each memory chip includes a phase detector configured to calibrate a phase relationship between a data-strobe signal and a clock signal received at the memory chip from the memory controller during a write operation. Furthermore, the memory controller is configured to perform one or more write-read-validate operations to calibrate a clock-cycle relationship between the data-strobe signal and the clock signal, wherein the write-read-validate operations involve varying a delay on the data-strobe signal relative to the clock signal by a multiple of a clock period.
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公开(公告)号：US20230395181A1
公开(公告)日：2023-12-07
申请号：US17831329
申请日：2022-06-02
CPC分类号： G11C29/52 , G11C29/023 , G11C29/021
摘要： A method can include detecting, by a glitch detector coupled via a connection matrix to a first processing unit, an indication of a glitch on a memory system. The method can include notifying, via the connection matrix, at least a second processing unit of the detected indication of the glitch. The method can include subsequent to notifying at least the second processing unit, transmitting via the at least the second processing unit a glitch confirmation signal.
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