公开(公告)号：US08860651B2

公开(公告)日：2014-10-14

申请号：US13458465

申请日：2012-04-27

Applicant: Chien-Chang Tseng ,  Kuang-Hsiang Liu ,  Yu-Hsin Ting ,  Shih-Hsiang Chou ,  Ting-Jui Chang

Inventor： Chien-Chang Tseng ,  Kuang-Hsiang Liu ,  Yu-Hsin Ting ,  Shih-Hsiang Chou ,  Ting-Jui Chang

IPC: G09G3/36

CPC classification number: G11C19/28 ,  G09G3/3674 ,  G09G2310/0286 ,  G09G2330/021

Abstract: A gate driver includes cascade-connected driving stages. Each of the driving stages includes a first shift register circuit and a second shift register circuit. The first shift register circuit is configured for outputting a present stage driving signal and a next stage driving signal. The second shift register circuit is electrically coupled to the first shift register circuit and configured for outputting a present stage gate signal, a first next stage gate signal, and a second next stage gate signal. Furthermore, a display panel is also provided herein.

Abstract translation: 门驱动器包括级联连接的驱动级。 每个驱动级包括第一移位寄存器电路和第二移位寄存器电路。 第一移位寄存器电路被配置为输出当前级驱动信号和下一级驱动信号。 第二移位寄存器电路电耦合到第一移位寄存器电路，并被配置为输出当前级门信号，第一下级门信号和第二下级门信号。 此外，还提供了显示面板。

公开(公告)号：US20130256706A1

公开(公告)日：2013-10-03

申请号：US13615598

申请日：2012-09-14

Applicant: Szu-Chieh Chen ,  Yu-Hsin Ting ,  Chen-Ming Chen ,  I-Fang Chen ,  Yi-Xuan Hung ,  Da-Wei Fan

Inventor： Szu-Chieh Chen ,  Yu-Hsin Ting ,  Chen-Ming Chen ,  I-Fang Chen ,  Yi-Xuan Hung ,  Da-Wei Fan

IPC: H01L33/08

CPC classification number: H01L27/124 ,  G02F1/1362 ,  G02F1/136213 ,  G02F1/13624 ,  G02F1/136286 ,  H01L27/1255

Abstract: A pixel array and a display panel are provided. The pixel array includes a plurality of pixel units. Each of the pixel units includes a first scan line, a second scan line, a data line, a first thin-film transistor, a second thin-film transistor, a first pixel electrode and a second pixel electrode. The first thin-film transistor is electrically connected to the first scan line and the data line. The first pixel electrode is electrically connected to the first thin-film transistor. The second thin-film transistor is electrically connected to the second scan line and the data line. The second pixel electrode is electrically connected to the second thin-film transistor. The orthogonal projection pattern of the first thin-film transistor on XY plane and the orthogonal projection pattern of the second thin-film transistor on XY plane are substantially the same.

公开(公告)号：US08305372B2

公开(公告)日：2012-11-06

申请号：US12490302

申请日：2009-06-23

Applicant: Yu-Hsin Ting ,  Tsao-Wen Lu

Inventor： Yu-Hsin Ting ,  Tsao-Wen Lu

IPC: G09G5/00

CPC classification number: G09G5/00 ,  G09G2330/027

Abstract: A display and a method for eliminating a residual image thereof are provided. The method includes detecting a status of an electric power supplied by a power supply unit of the display when the display is in the power on state; and coupling the electric power to a reference voltage when the electric power is suddenly terminated so as to accelerately discharge charges remaining on the electric power.

Abstract translation: 提供了一种用于消除其残留图像的显示器和方法。 该方法包括当显示器处于通电状态时检测由显示器的电源单元提供的电力的状态; 并且当电力突然终止时将电力耦合到参考电压，以便加速放电剩余在电力上的电荷。

公开(公告)号：US08263445B2

公开(公告)日：2012-09-11

申请号：US12652169

申请日：2010-01-05

Applicant: Yu-Hsin Ting

Inventor： Yu-Hsin Ting

IPC: H01L21/00

CPC classification number: G02F1/136213 ,  G02F1/136227 ,  H01L27/124 ,  H01L27/1255 ,  H01L27/3265

Abstract: A pixel structure comprising at least one transistor, a first storage capacitor, a first conductive layer, an interlayer dielectric layer, a second conductive layer, a passivation layer, and a third conductive layer is provided. The first storage capacitor is electrically connected to the transistor. The interlayer dielectric layer having at least one first opening covers the first conductive layer. The second conductive layer is formed on a part of the interlayer dielectric layer and is electrically connected to the first conductive layer through the first opening. The passivation layer having at least one second opening covers the transistor and the second conductive layer. The third conductive layer is formed on a part of the passivation layer and is electrically connected to the transistor through the second opening. The first storage capacitor is formed by the third conductive layer, the passivation layer, and the second conductive layer.

Abstract translation: 提供了包括至少一个晶体管，第一存储电容器，第一导电层，层间介电层，第二导电层，钝化层和第三导电层的像素结构。 第一存储电容器电连接到晶体管。 具有至少一个第一开口的层间绝缘层覆盖第一导电层。 第二导电层形成在层间电介质层的一部分上，并通过第一开口与第一导电层电连接。 具有至少一个第二开口的钝化层覆盖晶体管和第二导电层。 第三导电层形成在钝化层的一部分上，并通过第二开口与晶体管电连接。 第一存储电容器由第三导电层，钝化层和第二导电层形成。

公开(公告)号：US20110292005A1

公开(公告)日：2011-12-01

申请号：US12940765

申请日：2010-11-05

Applicant: Chee-Wai LAU ,  Yu-Hsin Ting ,  Chung-Lin Fu ,  Wei-Chun Hsu ,  Nan-Ying Lin ,  Fu-Yuan Liou

Inventor： Chee-Wai LAU ,  Yu-Hsin Ting ,  Chung-Lin Fu ,  Wei-Chun Hsu ,  Nan-Ying Lin ,  Fu-Yuan Liou

IPC: G09G5/00

CPC classification number: G09G3/3677 ,  G09G3/3688 ,  G09G2320/0257 ,  G09G2330/027

Abstract: A display apparatus includes a plurality of scan lines, a plurality of data lines, a plurality of pixel transistors, a plurality of pixel electrodes, a gate driver, a source driver and a discharge circuit. The data lines are intersected with the scan lines. Each of the pixel transistors is electrically coupled to a corresponding scan line and a corresponding data line, and each of the pixel electrodes is electrically coupled to a corresponding pixel transistor. The gate driver is electrically coupled to the scan lines, and the source driver is electrically coupled to the data lines. The discharge circuit is electrically coupled to the gate driver and the data lines. The discharge circuit starts when the display apparatus is turned off, to control the gate drive for turning on the pixel transistors simultaneously, and make the pixel electrodes be electrically communicated with a reference voltage.

Abstract translation: 显示装置包括多条扫描线，多条数据线，多个像素晶体管，多个像素电极，栅极驱动器，源极驱动器和放电电路。 数据线与扫描线相交。 每个像素晶体管电耦合到对应的扫描线和对应的数据线，并且每个像素电极电耦合到相应的像素晶体管。 栅极驱动器电耦合到扫描线，并且源极驱动器电耦合到数据线。 放电电路电耦合到栅极驱动器和数据线。 当显示装置关闭时，放电电路开始，同时控制栅极驱动以同时开启像素晶体，并使像素电极与基准电压电连通。

公开(公告)号：US07695874B2

公开(公告)日：2010-04-13

申请号：US11426388

申请日：2006-06-26

Applicant: Yen-Heng Huang ,  Yu-Wei Liu ,  Yu-Hsin Ting ,  Kuo-Yu Huang

Inventor： Yen-Heng Huang ,  Yu-Wei Liu ,  Yu-Hsin Ting ,  Kuo-Yu Huang

IPC: G02B5/20 ,  G02F1/1335

CPC classification number: G02B5/201 ,  G02B5/223 ,  G02F1/133516

Abstract: A color filter and a method for fabricating the same. At least one conductive film is provided above a light shielding layer between R/G/B color filter units. The conductive film is electrically connected to an electrode layer, thereby reducing the resistance thereof.

Abstract translation: 滤色器及其制造方法。 在R / G / B滤色器单元之间的遮光层上方设置至少一个导电膜。 导电膜电连接到电极层，从而降低其电阻。

公开(公告)号：US09007541B2

公开(公告)日：2015-04-14

申请号：US13615598

申请日：2012-09-14

Applicant: Szu-Chieh Chen ,  Yu-Hsin Ting ,  Chen-Ming Chen ,  I-Fang Chen ,  Yi-Xuan Hung ,  Da-Wei Fan

Inventor： Szu-Chieh Chen ,  Yu-Hsin Ting ,  Chen-Ming Chen ,  I-Fang Chen ,  Yi-Xuan Hung ,  Da-Wei Fan

IPC: G02F1/1362

CPC classification number: H01L27/124 ,  G02F1/1362 ,  G02F1/136213 ,  G02F1/13624 ,  G02F1/136286 ,  H01L27/1255

Abstract: A pixel array and a display panel are provided. The pixel array includes a plurality of pixel units. Each of the pixel units includes a first scan line, a second scan line, a data line, a first thin-film transistor, a second thin-film transistor, a first pixel electrode and a second pixel electrode. The first thin-film transistor is electrically connected to the first scan line and the data line. The first pixel electrode is electrically connected to the first thin-film transistor. The second thin-film transistor is electrically connected to the second scan line and the data line. The second pixel electrode is electrically connected to the second thin-film transistor. The orthogonal projection pattern of the first thin-film transistor on XY plane and the orthogonal projection pattern of the second thin-film transistor on XY plane are substantially the same.

Abstract translation: 提供像素阵列和显示面板。 像素阵列包括多个像素单元。 每个像素单元包括第一扫描线，第二扫描线，数据线，第一薄膜晶体管，第二薄膜晶体管，第一像素电极和第二像素电极。 第一薄膜晶体管电连接到第一扫描线和数据线。 第一像素电极电连接到第一薄膜晶体管。 第二薄膜晶体管电连接到第二扫描线和数据线。 第二像素电极电连接到第二薄膜晶体管。 XY平面上的第一薄膜晶体管的正交投影图案和XY平面上的第二薄膜晶体管的正交投影图案基本相同。

公开(公告)号：US08982031B2

公开(公告)日：2015-03-17

申请号：US13610900

申请日：2012-09-12

Applicant: Yi-Xuan Hung ,  Yu-Hsin Ting ,  Chen-Ming Chen ,  Szu-Chieh Chen ,  Da-Wei Fan ,  Chung-Lin Fu

Inventor： Yi-Xuan Hung ,  Yu-Hsin Ting ,  Chen-Ming Chen ,  Szu-Chieh Chen ,  Da-Wei Fan ,  Chung-Lin Fu

IPC: G09G3/36 ,  G09G3/20

CPC classification number: G09G3/20 ,  G09G2310/0218 ,  G09G2310/0275 ,  G09G2310/0281 ,  G09G2310/0297

Abstract: A display panel includes a plurality of first driving switches installed at a first side of the display panel, a plurality of second switches installed at a second side of the display panel, a plurality of first data lines, a plurality of second data lines, a plurality of scan lines, and a plurality of pixels. Each of the first driving switches includes a first input end and a plurality of first output ends. Each of the second driving switches includes a second input end and a plurality of second output ends. The first data lines are electrically connected to the first output ends. The second data lines are electrically connected to the second output ends. The plurality of pixels are electrically connected to the plurality of first data lines, second data lines and scan lines for displaying images. The first data lines and the second data lines are arranged interlacedly.

Abstract translation: 显示面板包括安装在显示面板的第一侧的多个第一驱动开关，安装在显示面板的第二侧的多个第二开关，多个第一数据线，多条第二数据线， 多个扫描线，以及多个像素。 每个第一驱动开关包括第一输入端和多个第一输出端。 每个第二驱动开关包括第二输入端和多个第二输出端。 第一数据线电连接到第一输出端。 第二数据线电连接到第二输出端。 多个像素电连接到多个第一数据线，第二数据线和用于显示图像的扫描线。 第一数据线和第二数据线被交错布置。

公开(公告)号：US20140035896A1

公开(公告)日：2014-02-06

申请号：US13567582

申请日：2012-08-06

Applicant: Nan-Ying Lin ,  Yu-Hsin Ting ,  Chung-Lin Fu ,  Wei-Chun Hsu ,  Pei-Hua Chen

Inventor： Nan-Ying Lin ,  Yu-Hsin Ting ,  Chung-Lin Fu ,  Wei-Chun Hsu ,  Pei-Hua Chen

IPC: G06F3/038

CPC classification number: G09G3/3611 ,  G09G3/3685 ,  G09G2310/0297

Abstract: In one aspect, an LCD includes a display panel with a pixel matrix having M scan lines and N data lines, and a multiplexer feed-through compensation circuit, which includes P signal lines for providing P video signals, P multiplexers, and K pairs of control lines providing K pairs of control signals. Each multiplexer is electrically coupled to a corresponding signal line and has K channels. Each channel includes first and second switches parallel-connected between the signal line and a corresponding data line for selectively transmitting the video signal to the corresponding data line. Each pair of control lines is respectively electrically coupled to the first and second switches of a corresponding channel of each multiplexer. Each pair of control signals are configured such that a time turning off one of the first and second switches is earlier than that turning off the other switch.

Abstract translation: 一方面，LCD包括具有M条扫描线和N条数据线的像素矩阵的显示面板和多路复用器馈通补偿电路，其包括用于提供P视频信号的P信号线，P多路复用器和K对 提供K对控制信号的控制线。 每个复用器电耦合到对应的信号线并且具有K个信道。 每个通道包括并联在信号线和相应的数据线之间的第一和第二开关，用于选择性地将视频信号传输到对应的数据线。 每对控制线分别电耦合到每个多路复用器的相应通道的第一和第二开关。 每对控制信号被配置为使得关闭第一和第二开关中的一个的时间早于关闭另一个开关的时间。

公开(公告)号：US20130135284A1

公开(公告)日：2013-05-30

申请号：US13458465

申请日：2012-04-27

Applicant: Chien-Chang TSENG ,  Kuang-Hsiang Liu ,  Yu-Hsin Ting ,  Shih-Hsiang Chou ,  Ting-Jui Chang

Inventor： Chien-Chang TSENG ,  Kuang-Hsiang Liu ,  Yu-Hsin Ting ,  Shih-Hsiang Chou ,  Ting-Jui Chang

IPC: G09G5/00

CPC classification number: G11C19/28 ,  G09G3/3674 ,  G09G2310/0286 ,  G09G2330/021

Abstract: A gate driver includes cascade-connected driving stages. Each of the driving stages includes a first shift register circuit and a second shift register circuit. The first shift register circuit is configured for outputting a present stage driving signal and a next stage driving signal. The second shift register circuit is electrically coupled to the first shift register circuit and configured for outputting a present stage gate signal, a first next stage gate signal, and a second next stage gate signal. Furthermore, a display panel is also provided herein.

Abstract translation: 门驱动器包括级联连接的驱动级。 每个驱动级包括第一移位寄存器电路和第二移位寄存器电路。 第一移位寄存器电路被配置为输出当前级驱动信号和下一级驱动信号。 第二移位寄存器电路电耦合到第一移位寄存器电路，并被配置为输出当前级门信号，第一下级门信号和第二下级门信号。 此外，还提供了显示面板。