公开(公告)号：US07995323B2

公开(公告)日：2011-08-09

申请号：US12172669

申请日：2008-07-14

申请人： Chung-Tsung Lu ,  Pin-Chia Su ,  Yu-Chih Liou

发明人： Chung-Tsung Lu ,  Pin-Chia Su ,  Yu-Chih Liou

IPC分类号： H01L21/683 ,  H01T23/00

CPC分类号： H01L21/6833

摘要： A wafer stage installed in a process chamber for safely dechucking a wafer is provided. In one embodiment, the wafer stage comprises: a chuck support for supporting a chuck; a chuck mounted on the chuck support for receiving and attaching a wafer thereto; a support lift means for supporting the wafer; a driving means coupled to the support lift means for gradually raising the support lift means to contact the wafer in response to a variable quantity; a controller for receiving the variable quantity; and a regulating means coupled to the driving means and to the controller, the regulating means for controlling the variable quantity going to the driving means when a predetermined variable quantity is detected.

摘要翻译： 提供了安装在用于安全地脱扣晶片的处理室中的晶片台。 在一个实施例中，晶片台包括：用于支撑卡盘的卡盘支撑件; 安装在卡盘支架上的用于接收和附接晶片的卡盘; 用于支撑晶片的支撑提升装置; 连接到所述支撑提升装置的驱动装置，用于逐渐升高所述支撑提升装置以响应于可变量与所述晶片接触; 用于接收可变量的控制器; 以及调节装置，其耦合到所述驱动装置和所述控制器，所述调节装置用于当检测到预定可变量时控制进入所述驱动装置的可变量。

公开(公告)号：US07101748B2

公开(公告)日：2006-09-05

申请号：US10788170

申请日：2004-02-26

申请人： Yu-Lung Yeh ,  Chu-We Hu ,  Li-Te Hsu ,  Pin-Chia Su

发明人： Yu-Lung Yeh ,  Chu-We Hu ,  Li-Te Hsu ,  Pin-Chia Su

IPC分类号： H01L21/8238

CPC分类号： H01L21/823814 ,  H01L27/0266

摘要： The fabrication an NMOS device featuring a shallow source/drain region, performed as part of an integrated process sequence employed to integrate the fabrication of other type devices with the fabrication of the NMOS device, has been developed. A critical feature of the integrated process sequence is the formation of the shallow source/drain region of the NMOS accomplished after formation of the other type devices, thus reducing the risk of exposure of the shallow source/drain region to possible damaging procedures used for the other type devices. In addition the process used to remove a photoresist shape, used to protect the completed other type devices from the shallow source/drain ion implantation procedure, has been modified again to reduce possible damage to the shallow source/drain region. The flow of CF4 in the plasma tool during the photoresist removing plasma ashing procedure, as well as the length of the post-plasma ashing wet clean procedure, have both been reduced resulting in reduced exposure of the shallow source/drain region to these procedures.

摘要翻译： 已经开发了制造具有浅源极/漏极区域的NMOS器件，其作为用于将其他类型器件的制造与NMOS器件的制造集成的集成工艺序列的一部分进行。 集成过程序列的关键特征是在形成其它类型器件之后形成NMOS的浅源/漏区，从而降低了浅源/漏区暴露于用于 其他类型的设备。 此外，用于去除用于保护完成的其它类型器件免于浅源/漏离子注入过程的光致抗蚀剂形状的方法已被再次修改，以减少对浅源/漏区的可能损坏。 在光致抗蚀剂去除等离子体灰化过程期间等离子体工具中的CF 4的流动以及后等离子体灰化湿法清洁程序的长度都被减少，导致浅的 源/漏区到这些程序。