公开(公告)号：US08532204B2

公开(公告)日：2013-09-10

申请号：US12860142

申请日：2010-08-20

Applicant: Sen Jiang

Inventor： Sen Jiang

IPC: H04L27/28

CPC classification number: H04L27/2618 ,  H04L27/0006 ,  H04L27/2614

Abstract: In an embodiment, a transmitter includes first and second processing blocks, which may each include hardware, software, or a combination of hardware and software. The first processing block is operable to generate a first peak-reducing vector. And the a second first processing block is operable to receive a first data vector, the data vector comprising a plurality of samples, the first data vector having a first peak with a first index and a first magnitude, a second peak with a second index and a second magnitude that is less than the first magnitude, and a first peak-to-average power ratio, and to generate a second data vector having a second peak-to-average power ratio that is lower than the first peak-to-average power ratio by using the first peak-reducing vector.

公开(公告)号：US20110158336A1

公开(公告)日：2011-06-30

申请号：US12860142

申请日：2010-08-20

Applicant: Sen JIANG

Inventor： Sen JIANG

IPC: H04L27/28

CPC classification number: H04L27/2618 ,  H04L27/0006 ,  H04L27/2614

Abstract: In an embodiment, a transmitter includes first and second processing blocks, which may each include hardware, software, or a combination of hardware and software. The first processing block is operable to generate a first peak-reducing vector. And the a second first processing block is operable to receive a first data vector, the data vector comprising a plurality of samples, the first data vector having a first peak with a first index and a first magnitude, a second peak with a second index and a second magnitude that is less than the first magnitude, and a first peak-to-average power ratio, and to generate a second data vector having a second peak-to-average power ratio that is lower than the first peak-to-average power ratio by using the first peak-reducing vector.

Abstract translation: 在一个实施例中，发射机包括第一和第二处理块，其可以各自包括硬件，软件或硬件和软件的组合。 第一处理块可操作以产生第一峰值减小向量。 第二处理块可操作以接收第一数据向量，所述数据向量包括多个样本，所述第一数据向量具有具有第一索引和第一幅度的第一峰值，具有第二索引和第二幅度的第二峰值 小于第一幅度和第一峰均功率比，并且通过以下方式生成具有低于第一峰均功率比的第二峰均功率比的第二数据矢量 使用第一降频矢量。

公开(公告)号：US07969946B2

公开(公告)日：2011-06-28

申请号：US12046246

申请日：2008-03-11

Applicant: Hongfei Zhu ,  Yanling Yao ,  Guobin Sun

Inventor： Hongfei Zhu ,  Yanling Yao ,  Guobin Sun

IPC: H04W4/00 ,  H04W36/00 ,  H04J3/16

CPC classification number: H04L1/187 ,  H04L1/1607 ,  H04W36/0011

Abstract: A mobile device includes a communications protocol stack including a MAC layer and TCP layer separated by an IP layer. A cross-layer coordination module parallel to the communications protocol stack is coupled to both the MAC layer and TCP layer. The MAC layer generates a message sent to the cross-layer coordination module indicating that the mobile device is about to engage in a communications handover from a first base station to a second base station. The cross-layer coordination module passes handover information to the TCP layer so as to inform the TCP layer of the communications handover. If the mobile device is operating as a TCP sender, the TCP layer freezes its connection and state during the communications handover. If the mobile device is operating as a TCP receiver, the TCP layer sends a TCP ACK message to a TCP sender having an advertised window size set to a zero value so as to cause the TCP sender to freeze a connection and state during communications handover.

Abstract translation: 移动设备包括通信协议栈，其包括由IP层分隔的MAC层和TCP层。 与通信协议栈并行的跨层协调模块耦合到MAC层和TCP层。 MAC层产生发送到跨层协调模块的消息，指示移动设备即将从第一基站到第二基站进行通信切换。 跨层协调模块将切换信息传递给TCP层，以通知TCP层通信切换。 如果移动设备作为TCP发送者运行，则TCP层在通信切换期间冻结其连接和状态。 如果移动设备作为TCP接收机操作，则TCP层向广播窗口大小设置为零值的TCP发送方发送TCP ACK消息，以使TCP发送者在通信切换期间冻结连接和状态。

公开(公告)号：US20100169617A1

公开(公告)日：2010-07-01

申请号：US12645767

申请日：2009-12-23

Applicant: Hong-Xia Sun ,  Kai-Feng Wang ,  Peng-Fei Zhu ,  Yong-Qiang Chris Wu

Inventor： Hong-Xia Sun ,  Kai-Feng Wang ,  Peng-Fei Zhu ,  Yong-Qiang Chris Wu

IPC: G06F9/00 ,  G06F9/40

CPC classification number: G06F9/3861 ,  G06F9/384

Abstract: A system for recovering an architecture register mapping table (ARMT). The system includes a first number of collection circuits and decode circuits, a second number of selection circuits, and an enable circuit. Information related to the mapping between each physical register and an appropriate architecture register is obtained from a physical register mapping table (PRMT) by one and only one collection circuit during only one of a fourth number of instruction cycles. Each decode circuit has its input coupled to the output of one different collection circuit and is capable of converting its input into a third number bit wide binary string selection code at its output. Each selection circuit is configured to receive from each selection code a bit from a bit position associated with that selection circuit. The enable circuit is configured to appropriately enable mapping of information from the PRMT to the ARMT.

Abstract translation: 一种用于恢复架构寄存器映射表（ARMT）的系统。 该系统包括第一数量的收集电路和解码电路，第二数量的选择电路和使能电路。 与每个物理寄存器和适当架构寄存器之间的映射相关的信息在仅在第四数量的指令周期中由唯一的一个采集电路从物理寄存器映射表（PRMT）获得。 每个解码电路的输入耦合到一个不同的采集电路的输出端，并且能够在其输出端将其输入转换为第三数位位宽的二进制串选择码。 每个选择电路被配置为从与该选择电路相关联的位位置从每个选择代码接收一位。 使能电路被配置为适当地启用从PRMT到ARMT的信息的映射。

公开(公告)号：US20100145969A1

公开(公告)日：2010-06-10

申请号：US12535615

申请日：2009-08-04

Applicant: Kai-Feng Wang ,  Hong-Xia Sun ,  Yong-Qiang Wu

Inventor： Kai-Feng Wang ,  Hong-Xia Sun ,  Yong-Qiang Wu

IPC: G06F17/30

CPC classification number: G06F9/38 ,  G06F7/02 ,  G06F9/3834 ,  G06F9/3855

Abstract: A comparison circuit can reduce the amount of power consumed when searching a load queue or a store queue of a microprocessor. Some embodiments of the comparison circuit use a comparison unit that performs an initial comparison of addresses using a subset of the address bits. If the initial comparison results in a match, a second comparison unit can be enabled to compare another subset of the address bits.

Abstract translation: 比较电路可以减少在搜索微处理器的加载队列或存储队列时消耗的功率量。 比较电路的一些实施例使用比较单元，其使用地址位的子集来执行地址的初始比较。 如果初始比较导致匹配，则可以使能第二比较单元来比较另一个地址比特的子集。

公开(公告)号：US12229370B2

公开(公告)日：2025-02-18

申请号：US18459249

申请日：2023-08-31

Applicant: STMICROELECTRONICS (BEIJING) R&D CO., LTD ,  STMICROELECTRONICS LTD

Inventor： Pengcheng Wen ,  Yuan Yun Wang

IPC: G06F3/041 ,  G06F3/044 ,  G09G3/3233

Abstract: A method of operating a display includes performing a non-synchronized touch scan pattern on a display with a controller coupled to the display. The non-synchronized touch scan pattern schedules touch scans independent of a refresh rate of the display. Upon the controller detecting a first synchronization pulse from a display controller coupled to the controller and the display, a first pulse-checking timer is started. Upon detecting a second synchronization pulse from the display controller and before the first pulse-checking timer expires, a first display refresh rate for the display is obtained from an interval between the first synchronization pulse and the second synchronization pulse. A synchronized touch scan pattern is performed with the controller, and is scheduled to avoid touch scans coinciding with refreshes of the display performed at the first display refresh rate.

公开(公告)号：US20230387845A1

公开(公告)日：2023-11-30

申请号：US17828413

申请日：2022-05-31

Applicant: STMICROELECTRONICS (BEIJING) R&D CO. LTD

Inventor： Na Zhang

IPC: H02P21/34 ,  H02P21/10

CPC classification number: H02P21/34 ,  H02P21/10 ,  H02P2207/055

Abstract: A method of starting a permanent magnet synchronous motor (PMSM) with field oriented control (FOC) includes: opening a first control loop of the PMSM; setting a first direction for a first current component of the PMSM; aligning a rotor of the PMSM to the first direction; after aligning the rotor, setting a second direction for the first current component, where the second direction is rotated from the first direction by 90 degrees; after setting the second direction, starting the rotor while the first control loop of the PMSM remains open; after starting the rotor, increasing a rotation speed of the rotor by operating the first control loop in a first closed-loop mode; and after increasing the rotation speed of the rotor, controlling the rotation speed of the rotor by operating the first control loop in a second closed-loop mode different from the first closed-loop mode.

公开(公告)号：US20170308220A1

公开(公告)日：2017-10-26

申请号：US15151247

申请日：2016-05-10

Applicant: STMicroelectronics Asia Pacific Pte Ltd ,  STMicroelectronics (Beijing) R&D Co. Ltd

Inventor： Tae-gil Kang ,  Hang Yin ,  Cam Chung La

IPC: G06F3/041 ,  G06F3/044

CPC classification number: G06F3/0416 ,  G06F3/044 ,  G06F3/04883 ,  G06F2203/04104 ,  G06F2203/04108

Abstract: An electronic device described herein includes a touch screen for a touch sensitive display carried by a portable housing. The electronic device is configured to operate in a high. detection threshold mode to determine whether an object is in contact with the touch sensitive display, and operate in a low detection threshold mode to determine whether the object is adjacent to the touch sensitive display, based on lack of detection of the object being in contact with the touch sensitive display. The electronic device is further configured to determine whether the object is in contact with a peripheral edge of the portable housing by determining whether the object is adjacent opposite sides of the touch sensitive display, based on detection of the object being adjacent to the touch sensitive display.

公开(公告)号：US09015450B2

公开(公告)日：2015-04-21

申请号：US12690719

申请日：2010-01-20

Applicant: Hong-Xia Sun ,  Peng Fei Zhu ,  Yong Qiang Wu

Inventor： Hong-Xia Sun ,  Peng Fei Zhu ,  Yong Qiang Wu

IPC: G06F15/00 ,  G06F9/30 ,  G06F9/40 ,  G06F9/38

CPC classification number: G06F9/30116 ,  G06F9/30123 ,  G06F9/384 ,  G06F9/3863

Abstract: Embodiments of a processor architecture efficiently implement shadow registers in hardware. A register system in a processor includes a set of physical data registers coupled to register renaming logic. The register renaming logic stores data in and retrieves data from the set of physical registers when the processor is in a first processor state. The register renaming logic identifies ones of the set of physical registers that have a first operational state as a first group of registers and identifies the remaining ones of the set of physical registers as a second group of registers in response to an indication that the processor is to enter a second processor state from the first processor state. The register renaming logic stores data in and retrieves data from the second group of registers but not the first group of registers when the processor is in the second processor state.

Abstract translation: 处理器架构的实施例在硬件中有效地实现影子寄存器。 处理器中的寄存器系统包括耦合到寄存器重命名逻辑的一组物理数据寄存器。 当处理器处于第一处理器状态时，寄存器重命名逻辑将数据存储在物理寄存器组中并从中检索数据。 寄存器重命名逻辑将具有第一操作状态的一组物理寄存器中的一个标识为第一组寄存器，并且响应于处理器的指示，将该组物理寄存器中剩余的一组物理寄存器识别为第二组寄存器 从第一处理器状态进入第二处理器状态。 当处理器处于第二处理器状态时，寄存器重命名逻辑将数据存储在第二组寄存器中，而不是第一组寄存器中的数据。

公开(公告)号：US20140122837A1

公开(公告)日：2014-05-01

申请号：US14064936

申请日：2013-10-28

Applicant: STMicroelectronics (Beijing) R&D Co. Ltd.

Inventor： Peng Fei Zhu ,  Hong-Xia Sun ,  Yong Qiang Wu

IPC: G06F9/30

CPC classification number: G06F9/3012 ,  G06F9/384

Abstract: Embodiments of a processor architecture utilizing multi-bank implementation of physical register mapping table are provided. A register renaming system to correlate architectural registers to physical registers includes a physical register mapping table and a renaming logic. The physical register mapping table has a plurality of entries each indicative of a state of a respective physical register. The mapping table has a plurality of non-overlapping sections each of which having respective entries of the mapping table. The renaming logic is coupled to search a number of the sections of the mapping table in parallel to identify entries that indicate the respective physical registers have a first state. The renaming logic selectively correlates each of a plurality of architectural registers to a respective physical register identified as being in the first state. Methods of utilizing the multi-bank implementation of physical register mapping table are also provided.

Abstract translation: 提供了利用多库实现物理寄存器映射表的处理器架构的实施例。 将结构寄存器与物理寄存器相关联的寄存器重命名系统包括物理寄存器映射表和重命名逻辑。 物理寄存器映射表具有多个表示每个物理寄存器的状态的条目。 映射表具有多个非重叠部分，每个部分具有映射表的相应条目。 重命名逻辑被耦合以并行地搜索映射表的多个部分以识别指示相应物理寄存器具有第一状态的条目。 重命名逻辑选择性地将多个体系结构寄存器中的每一个相关于被识别为处于第一状态的相应物理寄存器。 还提供了利用多库实现物理寄存器映射表的方法。