公开(公告)号：US20120173848A1

公开(公告)日：2012-07-05

申请号：US13340679

申请日：2011-12-30

Applicant: Hong Xia SUN ,  Yong Qiang WU ,  Kai Feng WANG ,  Peng Fei ZHU

Inventor： Hong Xia SUN ,  Yong Qiang WU ,  Kai Feng WANG ,  Peng Fei ZHU

IPC: G06F9/38 ,  G06F9/30

CPC classification number: G06F9/3826 ,  G06F9/3834 ,  G06F9/3861 ,  G06F9/3867

Abstract: An embodiment of an instruction pipeline includes first and second sections. The first section is operable to provide first and second ordered instructions, and the second section is operable, in response to the second instruction, to read first data from a data-storage location, is operable, in response to the first instruction, to write second data to the data-storage location after reading the first data, and is operable, in response to the writing the second data after reading the first data, to cause the flushing of a some, but not all, of the pipeline. Such an instruction pipeline may reduce the processing time lost and the energy expended due to a pipeline flush by flushing only a portion of the pipeline instead of flushing the entire pipeline.

Abstract translation: 指令流水线的实施例包括第一和第二部分。 第一部分可操作以提供第一和第二有序指令，并且第二部分响应于第二指令可操作地从数据存储位置读取第一数据，可响应于第一指令而可写入 在读取第一数据之后的第二数据到数据存储位置，并且可操作地，响应于在读取第一数据之后写入第二数据，以引起流水线的一些但不是全部的冲洗。 这种指令管道可以减少处理时间损失，并且由于通过仅冲洗管道的一部分而不是冲洗整个管道而由于管道冲洗而消耗的能量。

公开(公告)号：US20100169616A1

公开(公告)日：2010-07-01

申请号：US12631098

申请日：2009-12-04

Applicant: Kai-Feng WANG ,  Hong-Xia Sun ,  Peng-fei Zhu ,  Yong-qiang Wu

Inventor： Kai-Feng WANG ,  Hong-Xia Sun ,  Peng-fei Zhu ,  Yong-qiang Wu

IPC: G06F9/30

CPC classification number: G06F9/3836 ,  G06F9/3855

Abstract: An embodiment of a technique for selecting instructions for execution from an issue queue at multiple function units while reducing the chances of instruction collisions. Each function unit in a processor may include a selection logic circuit that selects a specific instruction from the issue queue for execution. In order to avoid instruction collision, a function unit may have a selection logic circuit that may select two instructions from an instruction queue: one according to a first selection technique and one according to a second selection technique. Then, by comparing the instruction selected by the first selection technique to the instruction selected by the selection logic circuit of another function unit, the instruction selected by the second technique may be used instead if there will be an instruction collision because the instruction selected by the first selection technique is the same as the instruction selected at a different function unit.

Abstract translation: 一种用于在减少指令冲突的机会的同时从多个功能单元的发布队列中选择用于执行的指令的技术的实施例。 处理器中的每个功能单元可以包括选择逻辑电路，其从发布队列中选择特定指令以供执行。 为了避免指令冲突，功能单元可以具有可以从指令队列中选择两个指令的选择逻辑电路：根据第一选择技术和第二选择技术的选择逻辑电路。 然后，通过将由第一选择技术选择的指令与由另一功能单元的选择逻辑电路选择的指令进行比较，可以使用由第二技术选择的指令来代替，否则将产生指令冲突，因为由 第一选择技术与在不同功能单元处选择的指令相同。

公开(公告)号：US09170817B2

公开(公告)日：2015-10-27

申请号：US12535590

申请日：2009-08-04

Applicant: Kai-Feng Wang ,  Hong-Xia Sun ,  Yong-Qiang Wu

Inventor： Kai-Feng Wang ,  Hong-Xia Sun ,  Yong-Qiang Wu

IPC: G06F9/38

CPC classification number: G06F9/3806 ,  G06F9/3844

Abstract: Some microprocessors check branch prediction information in a branch history table and/or a branch target buffer. To check for branch prediction information, a microprocessor can identify which instructions are control flow instructions and which instructions are non control flow instructions. To reduce power consumption in the branch history table and/or branch target buffer, the branch history table and/or branch target buffer can check for branch prediction information corresponding to the control flow instructions and not the non control flow instructions.

Abstract translation: 一些微处理器检查分支历史表和/或分支目标缓冲器中的分支预测信息。 为了检查分支预测信息，微处理器可以识别哪些指令是控制流程指令，哪些指令是非控制流程指令。 为了减少分支历史表和/或分支目标缓冲器中的功耗，分支历史表和/或分支目标缓冲器可以检查与控制流程指令相对应的分支预测信息，而不是非控制流程指令。

公开(公告)号：US20120173846A1

公开(公告)日：2012-07-05

申请号：US13325614

申请日：2011-12-14

Applicant: Kai Feng Wang ,  Peng Fei Zhu ,  Hong Xia Sun ,  Yong Qiang Wu

Inventor： Kai Feng Wang ,  Peng Fei Zhu ,  Hong Xia Sun ,  Yong Qiang Wu

IPC: G06F15/76 ,  G06F9/22

CPC classification number: G06F1/32

Abstract: In a network-on-chip (NoC) system, multiple data messages may be transferred among modules of the system. Power consumption due to the transfer of the messages may affect a cost and overall performance of the system. A described technique provides a way to reduce a volume of data transferred in the NoC system by exploiting redundancy of data messages. Thus, if a data message to be sent from a source in the NoC includes so-called “zero” bytes that are bytes including only bits set to “0,” such zero bytes may not be transmitted in the NoC. Information on whether each byte of the data message is a zero byte may be recorded in a storage such as a data structure. This information, together with non-zero bytes of the data message, may form a compressed version of the data message. The information may then be used to uncompress the compressed data message at a destination.

Abstract translation: 在片上网络（NoC）系统中，可以在系统的模块之间传送多个数据消息。 由于消息传送引起的功耗可能会影响系统的成本和整体性能。 所描述的技术提供了一种通过利用数据消息的冗余来减少在NoC系统中传送的数据量的方法。 因此，如果要从NoC中的源发送的数据消息包括仅包括设置为“0”的字节的所谓的“零”字节，那么这种零字节可能不会在NoC中发送。 关于数据消息的每个字节是否为零字节的信息可以被记录在诸如数据结构的存储器中。 该信息与数据消息的非零字节可以形成数据消息的压缩版本。 然后可以使用该信息来在目的地解压缩压缩数据消息。

公开(公告)号：US20100205409A1

公开(公告)日：2010-08-12

申请号：US12700638

申请日：2010-02-04

Applicant: Peng Fei Zhu ,  Hong-Xia Sun ,  Yong Qiang Wu

Inventor： Peng Fei Zhu ,  Hong-Xia Sun ,  Yong Qiang Wu

IPC: G06F9/30 ,  G06F1/04

CPC classification number: G06F9/3012 ,  G06F9/384

Abstract: Embodiments of a processor architecture utilizing multi-bank implementation of physical register mapping table are provided. A register renaming system to correlate architectural registers to physical registers includes a physical register mapping table and a renaming logic. The physical register mapping table has a plurality of entries each indicative of a state of a respective physical register. The mapping table has a plurality of non-overlapping sections each of which having respective entries of the mapping table. The renaming logic is coupled to search a number of the sections of the mapping table in parallel to identify entries that indicate the respective physical registers have a first state. The renaming logic selectively correlates each of a plurality of architectural registers to a respective physical register identified as being in the first state. Methods of utilizing the multi-bank implementation of physical register mapping table are also provided.

Abstract translation: 提供了利用多库实现物理寄存器映射表的处理器架构的实施例。 将结构寄存器与物理寄存器相关联的寄存器重命名系统包括物理寄存器映射表和重命名逻辑。 物理寄存器映射表具有多个表示每个物理寄存器的状态的条目。 映射表具有多个非重叠部分，每个部分具有映射表的相应条目。 重命名逻辑被耦合以并行地搜索映射表的多个部分以识别指示相应物理寄存器具有第一状态的条目。 重命名逻辑选择性地将多个体系结构寄存器中的每一个相关于被识别为处于第一状态的相应物理寄存器。 还提供了利用多库实现物理寄存器映射表的方法。

公开(公告)号：US09015450B2

公开(公告)日：2015-04-21

申请号：US12690719

申请日：2010-01-20

Applicant: Hong-Xia Sun ,  Peng Fei Zhu ,  Yong Qiang Wu

Inventor： Hong-Xia Sun ,  Peng Fei Zhu ,  Yong Qiang Wu

IPC: G06F15/00 ,  G06F9/30 ,  G06F9/40 ,  G06F9/38

CPC classification number: G06F9/30116 ,  G06F9/30123 ,  G06F9/384 ,  G06F9/3863

Abstract: Embodiments of a processor architecture efficiently implement shadow registers in hardware. A register system in a processor includes a set of physical data registers coupled to register renaming logic. The register renaming logic stores data in and retrieves data from the set of physical registers when the processor is in a first processor state. The register renaming logic identifies ones of the set of physical registers that have a first operational state as a first group of registers and identifies the remaining ones of the set of physical registers as a second group of registers in response to an indication that the processor is to enter a second processor state from the first processor state. The register renaming logic stores data in and retrieves data from the second group of registers but not the first group of registers when the processor is in the second processor state.

Abstract translation: 处理器架构的实施例在硬件中有效地实现影子寄存器。 处理器中的寄存器系统包括耦合到寄存器重命名逻辑的一组物理数据寄存器。 当处理器处于第一处理器状态时，寄存器重命名逻辑将数据存储在物理寄存器组中并从中检索数据。 寄存器重命名逻辑将具有第一操作状态的一组物理寄存器中的一个标识为第一组寄存器，并且响应于处理器的指示，将该组物理寄存器中剩余的一组物理寄存器识别为第二组寄存器 从第一处理器状态进入第二处理器状态。 当处理器处于第二处理器状态时，寄存器重命名逻辑将数据存储在第二组寄存器中，而不是第一组寄存器中的数据。

公开(公告)号：US08521991B2

公开(公告)日：2013-08-27

申请号：US12631098

申请日：2009-12-04

Applicant: Kai-feng Wang ,  Hong-Xia Sun ,  Peng-fei Zhu ,  Yong-qiang Wu

Inventor： Kai-feng Wang ,  Hong-Xia Sun ,  Peng-fei Zhu ,  Yong-qiang Wu

IPC: G06F9/30

CPC classification number: G06F9/3836 ,  G06F9/3855

Abstract: A technique for selecting instructions for execution from an issue queue at multiple function units while reducing the chances of instruction collisions. In an embodiment, each function unit in a processor may include a selection logic circuit that selects a specific instruction from the issue queue for execution. In order to avoid instruction collision, a function unit may have a selection logic circuit that may select two instructions from an instruction queue: one according to a first selection technique and one according to a second selection technique. Then, by comparing the instruction selected by the first selection technique to the instruction selected by the selection logic circuit of another function unit, the instruction selected by the second technique may be used instead if there will be an instruction collision because the instruction selected by the first selection technique is the same as the instruction selected at a different function unit.

Abstract translation: 一种用于在减少指令冲突的机会的同时从多个功能单元的问题队列中选择执行指令的技术。 在一个实施例中，处理器中的每个功能单元可以包括从发布队列中选择特定指令以供执行的选择逻辑电路。 为了避免指令冲突，功能单元可以具有可以从指令队列中选择两个指令的选择逻辑电路：根据第一选择技术和第二选择技术的选择逻辑电路。 然后，通过将由第一选择技术选择的指令与由另一功能单元的选择逻辑电路选择的指令进行比较，可以使用由第二技术选择的指令来代替，否则将产生指令冲突，因为由 第一选择技术与在不同功能单元处选择的指令相同。

公开(公告)号：US08291200B2

公开(公告)日：2012-10-16

申请号：US12535615

申请日：2009-08-04

Applicant: Kai-Feng Wang ,  Hong-Xia Sun ,  Yong-Qiang Wu

Inventor： Kai-Feng Wang ,  Hong-Xia Sun ,  Yong-Qiang Wu

IPC: G06F9/312 ,  G06F1/32

CPC classification number: G06F9/38 ,  G06F7/02 ,  G06F9/3834 ,  G06F9/3855

Abstract: A comparison circuit can reduce the amount of power consumed when searching a load queue or a store queue of a microprocessor. Some embodiments of the comparison circuit use a comparison unit that performs an initial comparison of addresses using a subset of the address bits. If the initial comparison results in a match, a second comparison unit can be enabled to compare another subset of the address bits.

Abstract translation: 比较电路可以减少在搜索微处理器的加载队列或存储队列时消耗的功率量。 比较电路的一些实施例使用比较单元，其使用地址位的子集来执行地址的初始比较。 如果初始比较导致匹配，则可以使能第二比较单元来比较另一个地址比特的子集。

公开(公告)号：US20120172681A1

公开(公告)日：2012-07-05

申请号：US13341013

申请日：2011-12-30

Applicant: Hong Xia SUN ,  Yong Qiang WU ,  Kai Feng WANG ,  Peng Fei ZHU

Inventor： Hong Xia SUN ,  Yong Qiang WU ,  Kai Feng WANG ,  Peng Fei ZHU

IPC: A61B5/0205 ,  A61B5/11

CPC classification number: G01P9/02 ,  A61B5/0022 ,  A61B5/01 ,  A61B5/0205 ,  A61B5/02438 ,  A61B5/067 ,  A61B5/1114 ,  A61B5/1115 ,  A61B5/1116 ,  A61B5/1117 ,  A61B5/113 ,  A61B5/6898 ,  A61B5/747 ,  G01C21/20 ,  G16H40/67

Abstract: An embodiment comprises includes an apparatus with a housing wearable by a subject and a first sensor operable to detect a position of the subject. An embodiment of the apparatus includes a second sensor operable to detect a body state of the subject, where the first body state may be a vital sign such as heart rate, blood pressure, body temperature or respiratory rate. The apparatus may also include a wireless module, and be operable to transmit body state data and position data to a remote device. The apparatus may include a gyroscope or an accelerometer, and may be operable to detect rotational change in the subject's position about and axis, linear acceleration of the subject along an axis, a change in position of the subject, or a rate of change in position of the subject.

Abstract translation: 一个实施例包括具有可由受试者穿戴的外壳的装置和可操作以检测被检者的位置的第一传感器。 该装置的实施例包括可操作以检测被检体的身体状态的第二传感器，其中第一身体状态可以是诸如心率，血压，体温或呼吸频率的生命体征。 该装置还可以包括无线模块，并且可操作以将身体状态数据和位置数据传送到远程设备。 该装置可以包括陀螺仪或加速度计，并且可以可操作以检测被摄体位置周围的轴的旋转变化，沿着轴的对象的线性加速度，对象的位置变化或位置的变化率 的主题。

公开(公告)号：US20120157769A1

公开(公告)日：2012-06-21

申请号：US13329293

申请日：2011-12-18

Applicant: Peng Fei Zhu ,  Yong Qiang Wu ,  Kai Feng Wang ,  Hong Xia Sun

Inventor： Peng Fei Zhu ,  Yong Qiang Wu ,  Kai Feng Wang ,  Hong Xia Sun

IPC: A61B1/04

CPC classification number: G01C19/02 ,  A61B1/00016 ,  A61B1/0002 ,  A61B1/00032 ,  A61B1/00057 ,  A61B1/00158 ,  A61B1/041 ,  A61B1/0661 ,  G01C19/00

Abstract: An embodiment comprises and apparatus having an image capture device with an image axis and a gyroscope operable to indicate the orientation of the image axis. An embodiment of a capsule endoscopy system comprises an imaging capsule and an external unit. The imaging capsule may comprise an image capture device having an image axis and a gyroscope operable to indicate the orientation of the image axis. The external unit may comprise a gyroscope operable to indicate an orientation of a subject and a harness wearable by a subject and operable to align the gyroscope with the subject. The imaging capsule may send and image to an external unit for processing and display, and the external unit may provide for calculation of the image-axis orientation relative to the body.

Abstract translation: 实施例包括具有图像轴的图像捕获装置和可操作以指示图像轴的取向的陀螺仪的装置。 胶囊内窥镜系统的实施例包括成像胶囊和外部单元。 成像胶囊可以包括具有图像轴的图像捕获装置和可操作以指示图像轴的取向的陀螺仪。 外部单元可以包括陀螺仪，其可操作以指示受试者的方位和由受试者佩戴的线束并可操作以将陀螺仪与对象对准。 成像胶囊可以发送和图像到外部单元进行处理和显示，并且外部单元可以提供相对于身体的图像轴取向的计算。