公开(公告)号：US20030065470A1

公开(公告)日：2003-04-03

申请号：US09968277

申请日：2001-09-28

发明人： Kenneth Mark Maxham

IPC分类号： G01R027/28 ,  G06F019/00

CPC分类号： G06F12/1009 ,  G06F12/1425

摘要： A method for in-service RAM testing in computer systems and networks having a virtual memory. The method involves identifying a number n of physical memory units pi, inull1 . . . n, in the RAM and a number nnull1 of virtual memory units vj, jnull1 . . . nnull1, in the virtual memory, performing a one-to-one mapping to map the physical memory units pi to virtual memory units vj such that a physical memory unit px is left unmapped, and then testing data in the unmapped physical memory unit px by destructive or non-destructive tests. After the test data from another physical memory unit py is copied to physical memory unit px and a one-to-one re-mapping of physical memory units pi to virtual memory units vj is performed such that physical memory unit py is left unmapped. The data in physical memory unit py is then tested and the steps of copying, one-to-one re-mapping and testing can be repeated until all physical memory units pi are tested. The testing can be performed with the aid of an MMU and it can involve more than one physical memory page at a time.

公开(公告)号：US20030028342A1

公开(公告)日：2003-02-06

申请号：US10200642

申请日：2002-07-22

发明人： Frank Adler ,  Martin Versen

IPC分类号： G06F019/00 ,  G01R027/28 ,  G01R031/00 ,  G01R031/14

CPC分类号： G11C29/56 ,  G11C5/04 ,  G11C29/56008 ,  G11C2029/4402 ,  G11C2029/5606

摘要： A computer system (2) which has at least one data defect memory (4), at least one address defect memory (5) and also a test program is connected to a memory module (7) which has a memory space with defect-free and defective memory cells, a plurality of data lines and also a plurality of address lines. The addresses of the defective memory cells in the memory space and also the data lines which are connected to the defective memory cells are determined from the information items of the address defect memory (5) and also from the information items of the data defect memory (4).

摘要翻译： 具有至少一个数据缺陷存储器（4），至少一个地址缺陷存储器（5）以及测试程序的计算机系统（2）被连接到具有无缺陷的存储器空间的存储器模块（7） 和有缺陷的存储单元，多条数据线以及多条地址线。 从地址缺陷存储器（5）的信息项以及数据缺陷存储器（5）的信息项中确定存储器空间中的有缺陷的存储单元的地址以及与缺陷存储单元相连的数据线 4）。

公开(公告)号：US20030014206A1

公开(公告)日：2003-01-16

申请号：US09878513

申请日：2001-06-11

申请人： ADC Telecommunications Israel Ltd.

发明人： Emanuel Gorodetsky ,  Eugeny Knupfer

IPC分类号： G06F019/00 ,  G01R027/28 ,  G01R031/00 ,  G01R031/14

CPC分类号： G06F17/5045 ,  G01R31/318583 ,  G06F11/27

摘要： A method of generating optimized netlists is provided. The method includes providing an input mechanism that is adapted to receive selective test report files from one or more circuit board test generation software programs and adapted to receive in-circuit test restriction parameters. The method further includes generating netlists based on the received test report files and in-circuit test restriction parameters. The netlists comprise one or more of total number of nets for the board, number of nets that do not require in-circuit test pads, number of nets that possibly require in-circuit test pads, number of in-circuit test pads as test points and edge connector terminals, and number of nets that require in-circuit test pads.

摘要翻译： 提供了一种生成优化网表的方法。 该方法包括提供适于从一个或多个电路板测试生成软件程序接收选择性测试报告文件并适于接收在线测试限制参数的输入机制。 该方法还包括基于接收的测试报告文件和在线测试限制参数生成网表。 网表包括电路板总数的一个或多个，不需要在线测试焊盘的网络数，可能需要在线测试焊盘的网络数，在线测试焊盘的数量作为测试点 和边缘连接器端子，以及需要在线测试焊盘的网络数量。

公开(公告)号：US20020196033A1

公开(公告)日：2002-12-26

申请号：US10138989

申请日：2002-05-02

发明人： Jon S. Martens

IPC分类号： G01R027/28

CPC分类号： G01R27/28 ,  H04B17/20

摘要： An S-parameter measurement technique allows measurement of devices under test (DUTs), such as power amplifiers, which require a modulated power tone drive signal for proper biasing, in combination with a probe tone test signal, wherein both the modulated and probe tone signals operate in the same frequency range. The technique uses a stochastic drive signal, such as a CDMA or WCDMA modulated signal in combination with a low power probe tone signal. A receiver in a VNA having a significantly narrower bandwidth than the modulated signal bandwidth enables separation of the modulated and probe tone signals. VNA calibration further improves the measurement accuracy. For modulated signals with a significant power level in the frequency range of the probe tone signal, ensemble averaging of the composite probe tone and power tone signals is used to enable separation of the probe tone signal for measurement.

摘要翻译： S参数测量技术允许测量被测设备（DUT），例如功率放大器，其需要调制功率音调驱动信号以进行适当的偏置，结合探测音测试信号，其中调制和探测音调信号 在相同的频率范围内工作。 该技术使用随机驱动信号，例如CDMA或WCDMA调制信号与低功率探测音调信号的组合。 具有比调制信号带宽明显更窄的带宽的VNA中的接收机能够分离调制和探测音调信号。 VNA校准进一步提高了测量精度。 对于在探测音信号的频率范围内具有显着功率电平的调制信号，使用复合探测音和功率乐音信号的整体平均来使探测音信号分离以进行测量。

公开(公告)号：US20020180459A1

公开(公告)日：2002-12-05

申请号：US09867799

申请日：2001-05-31

发明人： Veselin Skendzic ,  E. Frederick Bestel ,  Paul N. Stoving ,  William M. Hurst ,  Daniel Schreiber ,  Dan G. Margenian ,  Richard A. Harthun

IPC分类号： G01R027/28

CPC分类号： G01R15/06 ,  G01R15/18 ,  H01H33/027 ,  H01H33/666

摘要： Active crosstalk cancellation in a multi-phase system is achieved using a capacitive voltage divider for each phase in the multi-phase system. A voltage measurement is obtained for the desired phase and each additional phase of the multi-phase system. A product is generated for each additional phase by multiplying each additional phase voltage measurement by a corresponding predetermined constant. The product for each additional phase is subtracted from the voltage measurement of the desired phase.

摘要翻译： 使用多相系统中的每个相位的电容分压器来实现多相系统中的主动串扰消除。 对于多相系统的期望相位和每个附加相位，获得电压测量。 通过将每个附加相电压测量乘以相应的预定常数，为每个附加相产生乘积。 从所需相位的电压测量中减去每个附加相的乘积。

公开(公告)号：US20020158641A1

公开(公告)日：2002-10-31

申请号：US09984990

申请日：2001-11-01

发明人： Michael Stanimirov ,  Bernhard Deck ,  Walter Rueegg

IPC分类号： G01R027/28

CPC分类号： G01R15/181

摘要： The method described here makes it possible to determine the impedance of a line (1) by measuring the voltage (u) applied across the line and the time derivative of the current (i) flowing through the line. The measured values of the differentiated current are not integrated in this case, but rather are substituted directly, together with the measured voltage values, into an equation system from which the values of the inductance (L) and the resistance (R) of the line (1) can be estimated. In this way, integration of the values of the differentiated current is obviated.

摘要翻译： 这里描述的方法使得可以通过测量施加在该线路上的电压（u）和流过该线路的电流（i）的时间导数来确定线路（1）的阻抗。 在这种情况下，微分电流的测量值不会积分，而是直接与测量的电压值一起取代为方程式，其中电感（L）和电阻（R）的值由该系统 （1）可以估计。 以这种方式，消除了微分电流的值的积分。

公开(公告)号：US20020152047A1

公开(公告)日：2002-10-17

申请号：US10173245

申请日：2002-06-17

发明人： Hyang-Kyun Oh ,  Yishao Max Huang ,  Richard Brayden

IPC分类号： G06F019/00 ,  G01R027/28 ,  G01R031/00 ,  G01R031/14 ,  G01M019/00

CPC分类号： G06F13/4068 ,  G06F13/4081 ,  Y10S439/945

摘要： An integrated controller for the detection and operation of both PC Cards, smart cards and passive smart card adapter cards. In one aspect, the invention detects the presence of standard expansion cards or passive smart card adapters by utilizing the reserved detection and voltage selection signal area defined by the PC Card specification. In another aspect, the invention provides an integrated controller that includes logic to operate either a standard expansion card or a passive smart card adapter by reassigning certain PC Card signal lines to operate a standard expansion card or a passive smart card adapter, thereby eliminating the need to provide pins in addition to those defined by the PC Card specification.

摘要翻译： 一个用于检测和操作PC卡，智能卡和被动智能卡适配器卡的集成控制器。 一方面，本发明通过利用由PC卡规范定义的预留检测和电压选择信号区域来检测标准扩展卡或无源智能卡适配器的存在。 在另一方面，本发明提供了一种集成控制器，其包括通过重新分配某些PC卡信号线来操作标准扩展卡或被动智能卡适配器来操作标准扩展卡或被动智能卡适配器的逻辑，从而消除了需要 以提供除PC卡规范定义的引脚之外的引脚。

公开(公告)号：US20020147561A1

公开(公告)日：2002-10-10

申请号：US09828133

申请日：2001-04-09

发明人： William Baracat ,  Mark Brown ,  Brian Bartlebaugh ,  Lisa Ferrett ,  Fonda Fang Liu

IPC分类号： G06F019/00 ,  G01R027/28 ,  G01R031/00 ,  G01R031/14

CPC分类号： G01R31/318307 ,  G01R31/2834

摘要： A system and method for providing an intelligent wire testing capability for complex hardware systems. The system is comprised of a software application with a relational database interfacing with an automatic test equipment module. The relational database contains all of a system's architecture information plus all of the text and parametric information associated with the design. During a system test, the subject invention uses the wiring/system architecture as disclosed in the relational database together with an automatically generated test program to identify faults in a unit under test. Using the architecture knowledge, the subject invention is capable of automatically generating a wire harness schematic for printout or display on a CRT. The architecture knowledge also allows a technician to quickly distinguish between a broken wire and an unused pin in a connector. After the test, the observed values are stored in a testing results file for later review and trend analysis. Data from the trend analysis provides the technician with the data necessary to assess the state of the wiring in the UUT. At the completion of testing, the testing results file stays with the UUT thereby ensuring access to a complete testing history of the UUT at any time.

摘要翻译： 一种用于为复杂硬件系统提供智能线测试能力的系统和方法。 该系统由具有与自动测试设备模块接口的关系数据库的软件应用程序组成。 关系数据库包含系统的所有体系结构信息以及与设计相关的所有文本和参数信息。 在系统测试期间，本发明使用关系数据库中公开的布线/系统架构以及自动生成的测试程序来识别被测单元中的故障。 使用体系结构知识，本发明能够自动生成用于在CRT上打印或显示的线束原理图。 架构知识还允许技术人员快速区分连接器中的断线和未使用的引脚。 测试结束后，观察值存储在测试结果文件中，供以后查看和趋势分析。 来自趋势分析的数据为技术人员提供了评估UUT中接线状态所需的数据。 在测试完成后，测试结果文件与UUT保持一致，从而可以随时访问UUT的完整测试历史。

公开(公告)号：US20020077763A1

公开(公告)日：2002-06-20

申请号：US09745284

申请日：2000-12-20

发明人： Edward C.M. Chang ,  Derek S. Chang ,  Deirdre McGlashan

IPC分类号： G06F019/00 ,  G01R027/28

CPC分类号： G01R31/31709 ,  G01R31/3193

摘要： An automatic tester uses a coarse timing subsystem and a formatter circuit to generate a first formatted waveform with coarse timing based on the information stored in a vector memory subsystem. The first formatted waveform is refined by a timing refiner circuit to form a second formatted waveform with precise timing. The timing refiner circuit includes a flip-flop device to re-synchronize and remove jitter in the first formatted waveform. A counter and/or shift register and vernier circuit in the timing refiner circuit then triggers the leading and trailing edges of the second formatted waveform with precise timing. The formatter circuit may be eliminated by using control signals of the memory devices in the vector memory subsystem to manipulate timing. The coarse timing subsystem may further be eliminated by providing sufficient range for the counters in the timing refiner circuit.

摘要翻译： 自动测试仪使用粗定时子系统和格式器电路基于存储在向量存储器子系统中的信息来生成具有粗定时的第一格式化的波形。 第一格式化的波形由定时精炼器电路精炼以形成具有精确定时的第二格式化波形。 定时精磨机电路包括用于重新同步和去除第一格式化波形中的抖动的触发器装置。 定时精炼器电路中的计数器和/或移位寄存器和游标电路然后用精确的定时触发第二格式化波形的前沿和后沿。 可以通过使用向量存储器子系统中的存储器件的控制信号来消除格式器电路来操纵定时。 可以进一步通过为定时精磨机电路中的计数器提供足够的范围来消除粗定时子系统。

公开(公告)号：US20010025227A1

公开(公告)日：2001-09-27

申请号：US09812566

申请日：2001-03-21

发明人： Kazuyoshi Ajiro

IPC分类号： G06F019/00 ,  G01R027/28 ,  G01R031/00 ,  G01R031/14

CPC分类号： G06F11/24 ,  G01R31/30 ,  G01R31/31816 ,  G06F2201/83

摘要： A monitored burn-in test system and a monitored burn-in test method of microcomputers, which are capable of implementing the monitored burn-in test without increasing a load of software and improving the function of a tester unit. When microcomputers supply a tester unit with measurement data stored in a data compressing circuit comprised of a linear feedback resister, test data outputted by all of the microcomputers can be read synchronously into the tester unit by shifting out the measurement data synchronously with a monitoring clock signal outputted by the tester unit. Thus, it is made possible to monitor the test results of all microcomputers at the same time in the tester unit. Therefore, it can be avoided that a load of software gets heavier since the monitoring of the test results is certainly executed by the tester unit.

摘要翻译： 监控的老化测试系统和微型计算机的监控老化测试方法，可以在不增加软件负载并提高测试仪单元功能的情况下实现监控的老化测试。 当微型计算机向测试器单元提供存储在由线性反馈寄存器组成的数据压缩电路中的测量数据时，所有微型计算机输出的测试数据可以通过与监视时钟信号同步地移出测量数据而被同步地读入测试器单元 由测试器单元输出。 因此，可以在测试器单元中同时监视所有微型计算机的测试结果。 因此，可以避免软件负载变重，因为测试结果的监视肯定由测试器单元执行。