公开(公告)号：US08051237B2

公开(公告)日：2011-11-01

申请号：US11682230

申请日：2007-03-05

Applicant: Stuart Andrew Ryan ,  Andrew Michael Jones

Inventor： Stuart Andrew Ryan ,  Andrew Michael Jones

IPC: G06F13/36 ,  G06F1/00

CPC classification number: G06F11/004 ,  Y10T307/911

Abstract: An integrated circuit of the type comprises a plurality of units that may act as initiators and targets. At least some of the units are for a first purpose such as a cable modem function and others are for a second purpose such as television data processing. The units are connected together by a interconnect comprising a number of nodes. One of the nodes is configurable such that requests made from initiator units on one side of the node to target units on the other side of the node are not sent to the target units. The units for the first purpose are arranged on the opposite side of the node from those of the second purpose, so that the circuit is effectively configurable into two separate logical partitions, one partition for television data processing and the other partition for cable modem functions.

Abstract translation: 该类型的集成电路包括可用作发起者和目标的多个单元。 至少一些单元是用于电缆调制解调器功能的第一目的，而其他单元用于第二目的，例如电视数据处理。 这些单元通过包括多个节点的互连连接在一起。 节点之一是可配置的，使得从节点一侧的发起者单元到节点另一侧的目标单元的请求不发送到目标单元。 用于第一目的的单元被布置在与第二目的的节点的相对侧上，使得电路被有效地配置成两个单独的逻辑分区，用于电视数据处理的一个分区和用于电缆调制解调器功能的另一个分区。

公开(公告)号：US07895447B2

公开(公告)日：2011-02-22

申请号：US11020638

申请日：2004-12-22

Applicant: Andrew Dellow ,  Mark Owen Homewood

Inventor： Andrew Dellow ,  Mark Owen Homewood

IPC: G06F11/30 ,  G06F12/14

CPC classification number: G06F21/71 ,  G06F21/52

Abstract: A system and method for verifying the authenticity of instructions retrieved from a memory for execution by a processor. In one embodiment, an instruction monitor monitors execution parameters associated with the retrieved instruction and resets the system in response to an indication that an instruction is not authentic.

Abstract translation: 一种用于验证从存储器检索以由处理器执行的指令的真实性的系统和方法。 在一个实施例中，指令监视器监视与检索到的指令相关联的执行参数，并且响应于指令不可信的指示来重置系统。

公开(公告)号：US07889862B2

公开(公告)日：2011-02-15

申请号：US11523775

申请日：2006-09-18

Applicant: Andrew Dellow ,  Peter Bennett ,  Rodrigo Cordero

Inventor： Andrew Dellow ,  Peter Bennett ,  Rodrigo Cordero

IPC: H04L9/00

CPC classification number: H04N7/162 ,  G06F12/1408 ,  H04H60/23 ,  H04N7/1675

Abstract: A memory stores data in an encrypted form. A modifiable register stores a memory address, a0, defining a boundary separating the memory into two regions. The lower region stores data encrypted using a key B, and the upper region stores data encrypted using a different key A. Data stored on the boundary address is encrypted using key A. Accordingly, when data is read from a memory address a, key A is used to decrypt the data if a≧a0, and key B is used if a

Abstract translation: 内存以加密形式存储数据。 可修改的寄存器存储存储器地址a0，定义将存储器分为两个区域的边界。 下部区域存储使用密钥B加密的数据，上部区域存储使用不同的密钥A加密的数据。使用密钥A对存储在边界地址上的数据进行加密。因此，当从存储器地址a读取数据时，密钥A 如果a≥a0，则用于解密数据，如果a

公开(公告)号：US20100332528A1

公开(公告)日：2010-12-30

申请号：US12879830

申请日：2010-09-10

Applicant: Andrew R. Dellow

Inventor： Andrew R. Dellow

IPC: G06F17/30

CPC classification number: H04N21/462 ,  H04N5/76 ,  H04N5/913 ,  H04N21/4334 ,  H04N21/434 ,  H04N21/4408 ,  H04N2005/91364

Abstract: A device for locating a DES key value that corresponds to a packet identification (PID) contained at a variable possible location which comprises part only of a 32-bit packet header. A table stored in memory contains for each DES key: (i) a packet header having 32 bits with a PID of either 12, 9 or 8 bits contained at a defined location and with zero values elsewhere, and (ii) a mask value also having 32 bits with ones contained at the said defined location of the PID and zeros elsewhere. The table is divided into regions for respective packet format types. An incoming packet header at an input is combined with a first one of the mask values from the table to provide a combined value that consists of the value held in the input packet header at the defined location and zeros elsewhere. This combined value is compared with the corresponding packet header stored in the table. When they are not equal, the combining and comparison is repeated for the next row of the table. When they are equal, the corresponding DES key value is read from the table and provided as an output. The system can cope with variable PID formats within the packet header without alteration to the hardware but merely with re-programming of the table contents.

Abstract translation: 用于定位对应于包含在可变可能位置的分组标识（PID）的DES密钥值的设备，该可变位置仅包括32位分组报头的一部分。 存储在存储器中的表包含每个DES密钥：（i）具有32位的分组报头，其中包含在定义的位置处的12,9或8位的PID，并且在其他地方具有零值，以及（ii）掩码值 具有32位，其中包含在PID的所述定义的位置处，并且其他地方具有零。 该表被分成用于相应分组格式类型的区域。 在输入处的输入分组报头与表中的第一个掩码值组合，以提供组合值，该组合值由保存在定义位置的输入分组报头中的值和其他地方的零组成。 将该组合值与存储在表中的相应分组报头进行比较。 当它们不相等时，对于表的下一行重复组合和比较。 当它们相等时，从表中读取相应的DES密钥值作为输出。 该系统可以处理数据包头中的可变PID格式，而不会改变硬件，但只能对表内容进行重新编程。

公开(公告)号：US07839937B2

公开(公告)日：2010-11-23

申请号：US10167044

申请日：2002-06-11

Applicant: Rodrigo Cordero ,  Patrice Woodward

Inventor： Rodrigo Cordero ,  Patrice Woodward

IPC: H04B1/66

CPC classification number: H04N21/42615 ,  H04N21/426 ,  H04N21/434 ,  H04N21/4341 ,  H04N21/4345

Abstract: Circuitry for processing data includes a plurality of filters arranged in parallel. Input data is stored. The input data is applied to the plurality of filters to provide at least two parallel results. An operation is carried out with respect to the results.

Abstract translation: 用于处理数据的电路包括并排布置的多个滤波器。 输入数据被存储。 将输入数据应用于多个滤波器以提供至少两个并行结果。 对结果进行操作。

公开(公告)号：US07830432B2

公开(公告)日：2010-11-09

申请号：US11144112

申请日：2005-06-03

Applicant: Robert Henderson

Inventor： Robert Henderson

IPC: H04N3/14

CPC classification number: H04N5/37457 ,  H04N5/3741

Abstract: The image sensor includes an array of pixels. Each pixel has a pinned photodiode which transfers charge via a transfer gate to a floating diffusion, from which output is provided by a source follower. Each column has a voltage supply line and a signal line. Each row has a transfer gate control line, a read/reset control line, and a read/reset voltage line which receives alternately zero volts and a predetermined positive voltage from a decoder circuit.

Abstract translation: 图像传感器包括像素阵列。 每个像素具有钉扎光电二极管，其通过传输栅极将电荷传输到浮动扩散，从源极跟随器输出该输出。 每列具有电源线和信号线。 每行具有传输门控制线，读/复位控制线和从解码器电路交替接收零伏特和预定正电压的读/复电压线。

公开(公告)号：US07783894B2

公开(公告)日：2010-08-24

申请号：US10583577

申请日：2004-12-17

Applicant: Andrew Dellow ,  Howard Gurney

Inventor： Andrew Dellow ,  Howard Gurney

IPC: H04L29/06 ,  H04L9/32 ,  G06F11/30 ,  G06F12/14 ,  G06F17/00 ,  G06F11/00 ,  G06F12/16 ,  G08B23/00 ,  H04N7/16

CPC classification number: G06F21/72 ,  G06F12/1408 ,  G06F21/79 ,  G06F21/85

Abstract: A monolithic semiconductor integrated circuit is provided for selectively encrypting or decrypting data transmitted between one of a plurality of devices on the circuit and an external memory. Two series of data pathways connect the devices and the external memory. The first series of data pathways passes through a cryptographic circuit causing data to be encrypted or decrypted, and the other series of data pathways provides an unhindered route. When a data access request is made by a device, the data is selectively routed along one of the two series of data pathways according to the identification of the device making the data access request. In one example, if data is transmitted from a device to the external memory, the data is selectively encrypted before being stored in the external memory if the device transmitting the data is identified as secure. Then, when that data is retrieved from the external memory by a second device, the data is selectively decrypted only if the second device is identified as secure.

Abstract translation: 提供单片半导体集成电路，用于选择性地加密或解密在电路上的多个设备之一和外部存储器之间传输的数据。 两组数据通路连接设备和外部存储器。 数据路径的第一系列通过加密电路，导致数据被加密或解密，另一系列的数据路径提供了一个不受阻碍的路由。 当设备进行数据访问请求时，根据进行数据访问请求的设备的标识，数据沿着两个数据路径中的一个选择性地路由选择。 在一个示例中，如果数据从设备发送到外部存储器，则如果发送数据的设备被识别为安全的，则在被存储在外部存储器中之前，数据被选择性地加密。 然后，当通过第二设备从外部存储器检索数据时，只有当第二设备被识别为安全时才选择性地解密该数据。

公开(公告)号：US20100192031A1

公开(公告)日：2010-07-29

申请号：US12657228

申请日：2010-01-15

Applicant: Robert Warren

Inventor： Robert Warren

IPC: G01R31/3177 ,  G06F11/25

CPC classification number: G01R31/318563 ,  G01R31/318536

Abstract: An integrated circuit comprising (i) a plurality of portions, each portion including test control circuitry; and (ii) at least one test input arranged to receive test signals, the circuit having a test mode in which one or more of the plurality of portions are testable, wherein the circuit has a reset mode which has priority over the test mode.

Abstract translation: 一种集成电路，包括（i）多个部分，每个部分包括测试控制电路; 以及（ii）布置成接收测试信号的至少一个测试输入，所述电路具有其中所述多个部分中的一个或多个部分是可测试的测试模式，其中所述电路具有优于所述测试模式的重置模式。

公开(公告)号：US20100138706A1

公开(公告)日：2010-06-03

申请号：US12657642

申请日：2010-01-25

Applicant: Robert Warren

Inventor： Robert Warren

IPC: G01R31/3177 ,  G06F11/25

CPC classification number: G01R31/318555 ,  G01R31/318536 ,  G01R31/318552 ,  G01R31/318558 ,  G01R31/318563 ,  G01R31/3187

Abstract: An integrated circuit comprising: at least one test input for receiving test data; test control circuitry between the at least one test input and circuitry to be tested; wherein the test data is clocked in on a rising clock edge and a falling clock edge.

Abstract translation: 一种集成电路，包括：用于接收测试数据的至少一个测试输入; 所述至少一个测试输入和要测试的电路之间的测试控制电路; 其中测试数据在上升时钟沿和下降时钟沿被计时。

公开(公告)号：US07649560B2

公开(公告)日：2010-01-19

申请号：US11145438

申请日：2005-06-03

Applicant: Robert Henderson

Inventor： Robert Henderson

IPC: H04N3/14 ,  H01L31/113

CPC classification number: H04N9/045 ,  H04N5/37457 ,  H04N5/376

Abstract: A pinned-photodiode image sensor using shared output amplifiers, for example output amplifiers in the 2.5T arrangement has transfer gate control lines alternating or cross-coupled between successive columns or adjacent rows. This assists in removing row-row mismatches. In preferred embodiments, the approach is applied to Bayer pattern RGB sensors, and allows the gain and/or the exposure of green pixels to be controlled separately from those of red and blue pixels.

Abstract translation: 使用共享输出放大器（例如2.5T布置的输出放大器）的钉扎式光电二极管图像传感器具有在连续列或相邻行之间交替或交叉耦合的传输门控制线。 这有助于删除行行不匹配。 在优选实施例中，该方法应用于拜耳图案RGB传感器，并且允许与红色和蓝色像素的增益和/或绿色像素的曝光分开控制。