公开(公告)号：US20210343570A1

公开(公告)日：2021-11-04

申请号：US17372776

申请日：2021-07-12

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Brian Cronquist ,  Deepak C. Sekar

IPC: H01L21/683 ,  H01L21/822 ,  H01L23/525 ,  H01L27/10 ,  H01L27/105 ,  H01L27/108 ,  H01L27/112 ,  H01L29/66 ,  H01L21/74 ,  H01L27/02 ,  H01L27/11 ,  H01L27/118 ,  H01L21/762 ,  H01L21/768 ,  H01L21/8238 ,  H01L27/11551 ,  H01L29/792 ,  H01L27/092 ,  H01L27/11526 ,  H01L27/11529 ,  H01L29/423 ,  H01L29/78 ,  H01L27/06 ,  H01L27/12 ,  H01L29/788 ,  H01L21/84 ,  H01L27/11578 ,  H01L27/11573 ,  G11C8/16 ,  H01L23/48 ,  H01L25/065 ,  H01L23/00 ,  H01L25/00 ,  H01L23/367

Abstract: A method for producing a 3D memory device, the method comprising: providing a first level comprising a first single crystal layer; forming first alignment marks and control circuits comprising first single crystal transistors, wherein said control circuits comprise at least two metal layers; forming at least one second level above said control circuits; performing a first etch step within said second level; forming at least one third level above said at least one second level; performing a second etch step within said third level; and performing additional processing steps to form a plurality of first memory cells within said second level and a plurality of second memory cells within said third level, wherein said first etch step comprises performing a lithography step aligned to said first alignment marks.

公开(公告)号：US20210280499A1

公开(公告)日：2021-09-09

申请号：US17313986

申请日：2021-05-06

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Deepak C. Sekar ,  Brian Cronquist

IPC: H01L23/48 ,  H01L27/06 ,  H01L27/088 ,  H01L27/11551 ,  H01L27/108 ,  H01L29/732 ,  H01L27/11526 ,  H01L27/118 ,  H01L29/10 ,  H01L29/808 ,  H01L27/11573 ,  H01L29/66 ,  H01L27/02 ,  H01L27/11578 ,  H01L29/78 ,  H01L21/74 ,  H01L23/544 ,  H01L23/34 ,  H01L23/50

Abstract: A 3D semiconductor device, the device including: a first level including single crystal first transistors, and a first metal layer, where the first level is overlaid by a first isolation layer; a second level including second transistors, where the first isolation layer is overlaid by the second level, and where the second level is overlaid by a second isolation layer; a third level including single crystal third transistors, where the second isolation layer is overlaid by the third level, where the third level is overlaid by a third isolation layer, where the third level is bonded to the second isolation layer, and where the bonded includes at least one oxide to oxide bond.

公开(公告)号：US11107721B2

公开(公告)日：2021-08-31

申请号：US17145338

申请日：2021-01-10

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Brian Cronquist ,  Deepak C. Sekar

IPC: H01L27/11521 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11551 ,  H01L27/11578 ,  H01L21/683 ,  H01L21/74 ,  H01L21/762 ,  H01L21/768 ,  H01L21/822 ,  H01L21/8238 ,  H01L21/84 ,  H01L23/48 ,  H01L23/525 ,  H01L27/02 ,  H01L27/06 ,  H01L27/092 ,  H01L27/10 ,  H01L27/105 ,  H01L27/108 ,  H01L27/11 ,  H01L27/112 ,  H01L27/11526 ,  H01L27/11573 ,  H01L27/118 ,  H01L27/12 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/788 ,  H01L29/792 ,  G11C8/16 ,  H01L23/367 ,  H01L25/065 ,  H01L25/00 ,  H01L23/00

Abstract: A 3D semiconductor device, the device including: a first level including a single crystal layer and a plurality of first transistors; a first metal layer including interconnects between the plurality of first transistors, where the interconnects between the plurality of first transistors includes forming a plurality of logic gates; a plurality of second transistors atop at least a portion of the first metal layer, where at least six of the plurality of first transistors are connected in series forming at least a portion of a NAND logic structure, where the plurality of second transistors are vertically oriented transistors, and where the plurality of second transistors are at least partially directly atop of the NAND logic structure; and a second metal layer atop at least a portion of the plurality of second transistors, where the second metal layer is aligned to the first metal layer with less than 150 nm misalignment, and where at least one of the second transistors is a junction-less transistor.

公开(公告)号：US11094576B1

公开(公告)日：2021-08-17

申请号：US17246639

申请日：2021-05-01

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Brian Cronquist ,  Deepak C. Sekar

IPC: H01L21/683 ,  H01L21/74 ,  H01L21/762 ,  H01L21/768 ,  H01L21/822 ,  H01L21/8238 ,  H01L21/84 ,  H01L23/48 ,  H01L23/525 ,  H01L27/02 ,  H01L27/06 ,  H01L27/092 ,  H01L27/10 ,  H01L27/105 ,  H01L27/108 ,  H01L27/11 ,  H01L27/112 ,  H01L27/11526 ,  H01L27/11529 ,  H01L27/11551 ,  H01L27/11573 ,  H01L27/11578 ,  H01L27/118 ,  H01L27/12 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/788 ,  H01L29/792 ,  G11C8/16 ,  H01L23/367 ,  H01L25/065 ,  H01L25/00 ,  H01L23/00

Abstract: A method for producing a 3D memory device, the method including: providing a first level including a first single crystal layer; forming first alignment marks and control circuits including first single crystal transistors; forming at least one second level above the first level; performing a first etch step including etching first holes within the second level; forming at least one third level above the at least one second level; performing a second etch step including etching second holes within the third level; and performing additional processing steps to form a plurality of first memory cells within the second level and a plurality of second memory cells within the third level, where the etching first holes includes performing a lithography step aligned to the first alignment marks.

公开(公告)号：US11063071B1

公开(公告)日：2021-07-13

申请号：US17189201

申请日：2021-03-01

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Deepak C. Sekar ,  Brian Cronquist

IPC: H01L27/146 ,  H01L23/00 ,  H01L33/58 ,  H01L31/054

Abstract: A multi-level semiconductor device, the device including: a first level including integrated circuits; a second level including a structure designed to conduct electromagnetic waves in a confined manner, where the second level is disposed above the first level, where the first level includes crystalline silicon, where the second level includes crystalline silicon; and an oxide layer disposed between the first level and the second level, where the second level is bonded to the oxide layer, and where the bonded includes oxide to oxide bonds.

公开(公告)号：US20210210456A1

公开(公告)日：2021-07-08

申请号：US17189201

申请日：2021-03-01

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Deepak C. Sekar ,  Brian Cronquist

IPC: H01L23/00 ,  H01L27/146 ,  H01L33/58 ,  H01L31/054

Abstract: A multi-level semiconductor device, the device including: a first level including integrated circuits; a second level including a structure designed to conduct electromagnetic waves in a confined manner, where the second level is disposed above the first level, where the first level includes crystalline silicon, where the second level includes crystalline silicon; and an oxide layer disposed between the first level and the second level, where the second level is bonded to the oxide layer, and where the bonded includes oxide to oxide bonds.

公开(公告)号：US11024673B1

公开(公告)日：2021-06-01

申请号：US17121741

申请日：2020-12-14

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Deepak C. Sekar ,  Brian Cronquist

IPC: H01L27/24 ,  H01L27/06 ,  H01L27/108 ,  H01L27/11 ,  H01L27/11529 ,  H01L27/11551 ,  H01L27/11578 ,  H01L27/12 ,  H01L27/22 ,  H01L21/683 ,  H01L21/762 ,  H01L21/822 ,  H01L21/84 ,  H01L29/78 ,  H01L29/423 ,  H01L21/268 ,  H01L27/105 ,  H01L27/11526 ,  H01L27/11573 ,  H01L45/00

Abstract: A 3D semiconductor device, the device including: a first level including a single crystal layer, a first metal layer, a second metal layer above the first metal layer, and a third metal layer above the second metal layer, where the second metal layer is significantly thicker than either the third metal layer or the first metal layer, where the third metal layer is precisely aligned to the first metal layer with less than 20 nm misalignment; a second level including a first array of first memory cells, each of the first memory cells include first transistors; a third level including a second array of second memory cells, each of the second memory cells include second transistors, where the second level is above the third level, where the second transistors are self-aligned to the first transistors, being processed following the same lithography step; and periphery circuits connected by the second metal to control the memory cells, where the periphery circuits are either underneath or atop the memory cells.

公开(公告)号：US20210159109A1

公开(公告)日：2021-05-27

申请号：US17140381

申请日：2021-01-04

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Brian Cronquist ,  Deepak C. Sekar

IPC: H01L21/683 ,  H01L21/74 ,  H01L21/762 ,  H01L21/768 ,  H01L21/822 ,  H01L21/8238 ,  H01L21/84 ,  H01L23/48 ,  H01L23/525 ,  H01L27/02 ,  H01L27/06 ,  H01L27/092 ,  H01L27/10 ,  H01L27/105 ,  H01L27/108 ,  H01L27/11 ,  H01L27/112 ,  H01L27/11526 ,  H01L27/11529 ,  H01L27/11551 ,  H01L27/11573 ,  H01L27/11578 ,  H01L27/118 ,  H01L27/12 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/788 ,  H01L29/792 ,  G11C8/16

Abstract: A 3D semiconductor device, the device including: a first level including a first single crystal layer, the first level including first transistors, where the first transistors each include a single crystal channel; first metal layers interconnecting at least the first transistors; and a second level including a second single crystal layer, the second level including second transistors, where the second level overlays the first level, where the second transistors are horizontally oriented and each include a High-k metal gate, where the second level is bonded to the first level, and where the bonded includes oxide to oxide bonds.

公开(公告)号：US20210134645A1

公开(公告)日：2021-05-06

申请号：US17146416

申请日：2021-01-11

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Brian Cronquist ,  Deepak C. Sekar

IPC: H01L21/683 ,  H01L21/74 ,  H01L21/762 ,  H01L21/768 ,  H01L21/822 ,  H01L21/8238 ,  H01L21/84 ,  H01L23/48 ,  H01L23/525 ,  H01L27/02 ,  H01L27/06 ,  H01L27/092 ,  H01L27/10 ,  H01L27/105 ,  H01L27/108 ,  H01L27/11 ,  H01L27/112 ,  H01L27/11526 ,  H01L27/11529 ,  H01L27/11551 ,  H01L27/11573 ,  H01L27/11578 ,  H01L27/118 ,  H01L27/12 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/788 ,  H01L29/792 ,  G11C8/16

Abstract: A 3D semiconductor device, the device including: a first level including a plurality of first single crystal transistors and a first metal layer, where the first transistors include forming memory control circuits; a second level including a plurality of second transistors; a third level including a plurality of third transistors, where the second level is above the first level, and where the third level is above the second level; a second metal layer above the third level; and a third metal layer above the second metal layer, where the second transistors are aligned to the first transistors with less than 140 nm alignment error, where the second level includes a plurality of first memory cells, where the third level includes a plurality of second memory cells, and where the memory control circuits are designed to adjust a memory write voltage according to the device specific process parameters

公开(公告)号：US20210134644A1

公开(公告)日：2021-05-06

申请号：US17145678

申请日：2021-01-11

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Brian Cronquist ,  Deepak C. Sekar

IPC: H01L21/683 ,  H01L21/74 ,  H01L21/762 ,  H01L21/768 ,  H01L21/822 ,  H01L21/8238 ,  H01L21/84 ,  H01L23/48 ,  H01L23/525 ,  H01L27/02 ,  H01L27/06 ,  H01L27/092 ,  H01L27/10 ,  H01L27/105 ,  H01L27/108 ,  H01L27/11 ,  H01L27/112 ,  H01L27/11526 ,  H01L27/11529 ,  H01L27/11551 ,  H01L27/11573 ,  H01L27/11578 ,  H01L27/118 ,  H01L27/12 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/788 ,  H01L29/792 ,  G11C8/16

Abstract: A 3D semiconductor device including: a first level including logic circuits, the logic circuits include a plurality of first single crystal transistors and a first metal layer; a second level including a plurality of second transistors, where the second level includes memory cells including the plurality of second transistors; a second metal layer atop the second level; where the plurality of second transistors are junction-less transistors, where at least one of the plurality of second transistors includes polysilicon, where the memory cells are structured as a plurality of at least sixteen sub-arrays, where each of the sub-arrays is independently controlled, where at least one of the plurality of at least sixteen sub-arrays is at least partially atop at least one of the logic circuits, and where the at least one of the logic circuits is designed to control at least one of the plurality of at least sixteen sub-arrays.