公开(公告)号：US20240323401A1

公开(公告)日：2024-09-26

申请号：US18734115

申请日：2024-06-05

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Kiyofumi Abe ,  Takahiro Nishi ,  Tadamasa Toma ,  Ryuichi Kanoh

IPC: H04N19/159 ,  H04N19/105 ,  H04N19/176 ,  H04N19/186 ,  H04N19/583

CPC classification number: H04N19/159 ,  H04N19/105 ,  H04N19/176 ,  H04N19/186 ,  H04N19/583

Abstract: An encoder includes memory, and circuitry accessible to the memory. The circuitry accessible to the memory: determines whether OBMC is applicable to generation of a prediction image of a current block, according to whether BIO is to be applied to the generation of the prediction image of the current block; when BIO is to be applied to the generation of the prediction image of the current block, determines that OBMC is not applicable to the generation of the prediction image of the current block, and applies BIO to the generation of the prediction image of the current block without applying OBMC.

公开(公告)号：US12081752B2

公开(公告)日：2024-09-03

申请号：US17728286

申请日：2022-04-25

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Kiyofumi Abe ,  Takahiro Nishi ,  Tadamasa Toma ,  Ryuichi Kanoh ,  Chong Soon Lim ,  Ru Ling Liao ,  Hai Wei Sun ,  Sughosh Pavan Shashidhar ,  Han Boon Teo ,  Jing Ya Li

IPC: H04N19/119 ,  H04N19/176

CPC classification number: H04N19/119 ,  H04N19/176

Abstract: Provided is an encoder which includes circuitry and memory. The circuitry encodes an image block using the memory. In encoding the image block, the circuitry: obtains one or more size parameters related to a size of the image block; determines whether the one or more size parameters and one or more thresholds satisfy a determined relationship; encodes a split parameter when the one or more size parameters and the one or more thresholds are determined to satisfy the determined relationship, the split parameter indicating whether the image block is to be split into a plurality of partitions including a non-rectangular partition; and encodes the image block after splitting the image block into the plurality of partitions when the split parameter indicates that the image block is to be split into the plurality of partitions.

公开(公告)号：US12075070B2

公开(公告)日：2024-08-27

申请号：US17681105

申请日：2022-02-25

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Virginie Drugeon ,  Tadamasa Toma ,  Takahiro Nishi ,  Kiyofumi Abe ,  Yusuke Kato

IPC: H04N19/30 ,  H04N19/103 ,  H04N19/157 ,  H04N19/169 ,  H04N19/70

CPC classification number: H04N19/30 ,  H04N19/103 ,  H04N19/157 ,  H04N19/188 ,  H04N19/70

Abstract: An encoder includes: memory; and circuitry coupled to the memory and configured to generate an encoded bitstream. In the encoder, when a multi-layer structure is to be included in the encoded bitstream to be generated, the circuitry generates the encoded bitstream by including in the encoded bitstream (i) a sequence parameter set that refers to a video parameter set and (ii) a network abstraction layer (NAL) unit having a layer identification (ID) greater than zero in the multi-layer structure, and when the multi-layer structure is not to be included in the encoded bitstream to be generated, the circuitry generates the encoded bitstream by including in the encoded bitstream a sequence parameter set that does not refer to the video parameter set.

公开(公告)号：US12069303B2

公开(公告)日：2024-08-20

申请号：US18242846

申请日：2023-09-06

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Chong Soon Lim ,  Han Boon Teo ,  Takahiro Nishi ,  Tadamasa Toma ,  Ru Ling Liao ,  Sughosh Pavan Shashidhar ,  Hai Wei Sun

IPC: H04N19/597 ,  G06T5/80 ,  H04N5/00 ,  H04N19/159 ,  H04N19/176 ,  H04N19/46 ,  H04N19/85

CPC classification number: H04N19/597 ,  G06T5/80 ,  H04N19/159 ,  H04N19/176 ,  H04N19/46 ,  H04N19/85

Abstract: An encoder capable of properly handling an image to be encoded or decoded includes processing circuitry and memory connected to the processing circuitry. Using the memory, the processing circuitry: obtains parameters including at least one of (i) one or more parameters related to a first process for correcting distortion in an image captured with a wide angle lens and (ii) one or more parameters related to a second process for stitching a plurality of images; generates an encoded image by encoding a current image to be processed that is based on the image or the plurality of images; and writes the parameters into a bitstream including the encoded image.

公开(公告)号：US12063358B2

公开(公告)日：2024-08-13

申请号：US18196763

申请日：2023-05-12

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Tadamasa Toma ,  Takahiro Nishi ,  Kiyofumi Abe ,  Yusuke Kato

IPC: H04N19/105 ,  H04N19/176 ,  H04N19/182

CPC classification number: H04N19/105 ,  H04N19/176 ,  H04N19/182

Abstract: An encoder includes circuitry and memory connected to the circuitry. The circuitry, in operation: derives, as a first parameter, a total sum of absolute values of sums of horizontal gradient values respectively for pairs of relative pixel positions; derives, as a second parameter, a total sum of absolute values of sums of vertical gradient values respectively for the pairs of relative pixel positions; derives, as a third parameter, a total sum of horizontal-related pixel difference values respectively for the pairs of relative pixel positions; derives, as a fourth parameter, a total sum of vertical-related pixel difference values respectively for the pairs of relative pixel positions; derives, as a fifth parameter, a total sum of vertical-related sums of horizontal gradient values respectively for the pairs of relative pixel positions; and generates a prediction image to be used to encode the current block using the first, second, third, fourth, and fifth parameters.

公开(公告)号：US20240259522A1

公开(公告)日：2024-08-01

申请号：US18629174

申请日：2024-04-08

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Han Boon Teo ,  Chong Soon Lim ,  Jingying Gao ,  Praveen Kumar Yadav ,  Kiyofumi Abe ,  Takahiro Nishi ,  Tadamasa Toma

IPC: H04N7/01 ,  H04N19/184 ,  H04N19/70

CPC classification number: H04N7/013 ,  H04N19/184 ,  H04N19/70

Abstract: An encoder includes circuitry and memory coupled to the circuitry. In operation, the circuitry encodes a video into a bitstream, the video is specified to be outputted at a first speed different from an original speed of the video, and in encoding the video, the circuitry encodes, into the bitstream, original speed information related to a second speed that is the original speed of the video.

公开(公告)号：US12047587B2

公开(公告)日：2024-07-23

申请号：US18135997

申请日：2023-04-18

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Kiyofumi Abe ,  Takahiro Nishi ,  Tadamasa Toma ,  Ryuichi Kanoh

IPC: H04N19/159 ,  H04N19/105 ,  H04N19/176 ,  H04N19/186 ,  H04N19/583

CPC classification number: H04N19/159 ,  H04N19/105 ,  H04N19/176 ,  H04N19/186 ,  H04N19/583

Abstract: An encoder includes memory, and circuitry accessible to the memory. The circuitry accessible to the memory: determines whether OBMC is applicable to generation of a prediction image of a current block, according to whether BIO is to be applied to the generation of the prediction image of the current block; when BIO is to be applied to the generation of the prediction image of the current block, determines that OBMC is not applicable to the generation of the prediction image of the current block, and applies BIO to the generation of the prediction image of the current block without applying OBMC.

公开(公告)号：US20240214604A1

公开(公告)日：2024-06-27

申请号：US18598487

申请日：2024-03-07

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Kiyofumi Abe ,  Takahiro Nishi ,  Tadamasa Toma

IPC: H04N19/52 ,  H04N19/176 ,  H04N19/186

CPC classification number: H04N19/52 ,  H04N19/176 ,  H04N19/186

Abstract: An encoder includes circuitry and memory connected to the circuitry. In operation, the circuitry: stores MV information and correction processing information into a FIFO buffer for an HMVP mode in association, the MV information being derived for a processed block and correction processing information being related to correction processing of a prediction image of the processed block; registers, in a prediction candidate list for a merge mode, one or more prediction candidates each being a combination of MV information and correction processing information, the prediction candidates including a prediction candidate which is a combination of the motion vector information and the correction processing information stored in the FIFO buffer; and selects a prediction candidate from the prediction candidate list when a current block is to be processed in the merge mode, and performs correction processing of a prediction image of the current block, based on the correction processing information.

公开(公告)号：US12015764B2

公开(公告)日：2024-06-18

申请号：US17585833

申请日：2022-01-27

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Takahiro Nishi ,  Tadamasa Toma ,  Kiyofumi Abe ,  Yusuke Kato

IPC: H04N19/105 ,  H04N19/172 ,  H04N19/174 ,  H04N19/46

CPC classification number: H04N19/105 ,  H04N19/172 ,  H04N19/174 ,  H04N19/46

Abstract: An encoder includes circuitry and memory coupled to the circuitry. In operation, the circuitry encodes, into a sequence parameter set, a first parameter indicating that a change in a picture size is allowed for any of pictures, determines whether or not a reference picture having a same size as a current picture is available to encode the current picture, and disables temporal motion vector prediction when it is determined that the reference picture having the same size as the current picture is not available.

公开(公告)号：US11997271B2

公开(公告)日：2024-05-28

申请号：US17987633

申请日：2022-11-15

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Tadamasa Toma ,  Takahiro Nishi ,  Kiyofumi Abe ,  Ryuichi Kanoh ,  Chong Soon Lim ,  Sughosh Pavan Shashidhar ,  Ru Ling Liao ,  Hai Wei Sun ,  Han Boon Teo ,  Jing Ya Li

IPC: H04N19/119 ,  H04N19/157 ,  H04N19/176

CPC classification number: H04N19/119 ,  H04N19/157 ,  H04N19/176

Abstract: An encoder partitions into blocks using a set of block partition modes. The set of block partition modes includes a first partition mode for partitioning a first block, and a second block partition mode for partitioning a second block which is one of blocks obtained after the first block is partitioned. When the number of partitions of the first block partition mode is three, the second block is a center block among the blocks obtained after partitioning the first block, and the partition direction of the second block partition mode is same as the partition direction of the first block partition mode, the second block partition mode indicates that the number of partitions is only three. A parameter for identifying the second block partition mode includes a first flag indicating a horizontal or vertical partition direction, and does not include a second flag indicating the number of partitions.