公开(公告)号：US10296393B2

公开(公告)日：2019-05-21

申请号：US15269957

申请日：2016-09-19

Applicant: Texas Instruments Incorporated

Inventor： Niraj Nandan ,  Hetul Sanghvi ,  Mihir Narendra Mody

IPC: G06F9/46 ,  G06F9/50 ,  G06F9/48 ,  G06F9/52 ,  G06F11/07

Abstract: A hardware thread scheduler (HTS) is provided for a multiprocessor system. The HTS is configured to schedule processing of multiple threads of execution by resolving data dependencies between producer modules and consumer modules for each thread. Pattern adaptors may be provided in the scheduler that allows mixing of multiple data patterns across blocks of data. Transaction aggregators may be provided that allow re-using the same image data by multiple threads of execution while the image date remains in a given data buffer. Bandwidth control may be provided using programmable delays on initiation of thread execution. Failure and hang detection may be provided using multiple watchdog timers.

公开(公告)号：US20190073740A1

公开(公告)日：2019-03-07

申请号：US15695266

申请日：2017-09-05

Applicant: Texas Instruments Incorporated

Inventor： Hrushikesh Tukaram Garud ,  Ankit Ajmani ,  Soyeb Noormohammed Nagori ,  Mihir Narendra Mody

IPC: G06T1/20 ,  G06T1/60

Abstract: A computer vision system is provided that includes a camera capture component configured to capture an image from a camera, a memory, and an image compression decompression engine (ICDE) coupled to the memory and configured to receive each line of the image, and compress each line to generate a compressed bit stream. To compress a line, the ICDE is configured to divide the line into compression units, and compress each compression unit, wherein to compress a compression unit, the ICDE is configured to perform delta prediction on the compression unit to generate a delta predicted compression unit, compress the delta predicted compression unit using exponential Golomb coding to generate a compressed delta predicted compression unit, and add the compressed delta predicted compression unit to the compressed bit stream.

公开(公告)号：US20190005656A1

公开(公告)日：2019-01-03

申请号：US15638123

申请日：2017-06-29

Applicant: Texas Instruments Incorporated

Inventor： Hetul Sanghvi ,  Mihir Narendra Mody ,  Niraj Nandan ,  Anish Reghunath ,  Michael Peter Lachmayr

IPC: G06T7/246 ,  G06T7/20 ,  G06T7/269

CPC classification number: G06T7/251 ,  G06T7/20 ,  G06T7/246 ,  G06T7/269 ,  G06T2207/10016 ,  G06T2207/10028 ,  G06T2207/30252 ,  G06T2207/30261

Abstract: A computer vision system is provided that includes an image generation device configured to generate consecutive two dimensional (2D) images of a scene, and a dense optical flow engine (DOFE) configured to determine a dense optical flow map for pairs of the consecutive 2D images, wherein, for a pair of consecutive 2D images, the DOFE is configured to perform a predictor based correspondence search for each paxel in a current image of the pair of consecutive 2D images, wherein, for an anchor pixel in each paxel, the predictor based correspondence search evaluates a plurality of predictors to select a best matching pixel in a reference image of the pair of consecutive 2D images, and determine optical flow vectors for each pixel in a paxel based on the best matching pixel selected for the anchor pixel of the paxel.

公开(公告)号：US09967569B2

公开(公告)日：2018-05-08

申请号：US15367378

申请日：2016-12-02

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Hrushikesh Tukaram Garud ,  Mihir Narendra Mody ,  Soyeb Nagori

IPC: H04N19/147 ,  H04N19/82 ,  H04N19/117 ,  H04N19/182 ,  H04N19/149 ,  H04N19/176

CPC classification number: H04N19/147 ,  H04N19/117 ,  H04N19/149 ,  H04N19/176 ,  H04N19/182 ,  H04N19/82

Abstract: The disclosure provides a sample adaptive offset (SAO) encoder. The SAO encoder includes a statistics collection (SC) block and a rate distortion optimization (RDO) block coupled to the SC block. The SC block receives a set of deblocked pixels and a set of original pixels. The SC block categorizes each deblocked pixel of the set of deblocked pixels in at least one of a plurality of band and edge categories. The SC block estimates an error in each category as difference between a deblocked pixel of the set of deblocked pixels and corresponding original pixel of the set of original pixels. The RDO block determines a set of candidate offsets associated with each category and selects a candidate offset with a minimum RD cost. The minimum RD cost is used by a SAO type block and a decision block to generate final offsets for the SAO encoder.

公开(公告)号：US09906815B2

公开(公告)日：2018-02-27

申请号：US13671344

申请日：2012-11-07

Applicant: Texas Instruments Incorporated

Inventor： Ranga Ramanujam Srinivasan ,  Chaitanya Satish Ghone ,  Mihir Narendra Mody ,  Minhua Zhou

IPC: H04N7/32 ,  H04N19/895 ,  H04N19/172 ,  H04N19/107 ,  H04N19/39 ,  H04N19/65

CPC classification number: H04N19/895 ,  H04N19/107 ,  H04N19/172 ,  H04N19/39 ,  H04N19/65

Abstract: A method is provided that includes receiving pictures of a video sequence in a video encoder, and encoding the pictures to generate a compressed video bit stream that is transmitted to a video decoder in real-time, wherein encoding the pictures includes selecting a picture to be encoded as a delayed duplicate intra-predicted picture (DDI), wherein the picture would otherwise be encoded as an inter-predicted picture (P-picture), encoding the picture as an intra-predicted picture (I-picture) to generate the DDI, wherein the I-picture is reconstructed and stored for use as a reference picture for a decoder refresh picture, transmitting the DDI to the video decoder in non-real time, selecting a subsequent picture to be encoded as the decoder refresh picture, and encoding the subsequent picture in the compressed bit stream as the decoder refresh picture, wherein the subsequent P-picture is encoded as a P-picture predicted using the reference picture.

公开(公告)号：US20170311002A1

公开(公告)日：2017-10-26

申请号：US15646258

申请日：2017-07-11

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Mihir Narendra Mody ,  Chaitanya S Ghone ,  Joseph Meehan

IPC: H04N19/86 ,  H04N19/42 ,  H04N19/44 ,  H04N19/82

CPC classification number: H04N19/86 ,  H04N19/42 ,  H04N19/44 ,  H04N19/82

Abstract: A VP8 video decoder is implemented by partitioning the required functions across multiple sub systems, with an optimal mapping to existing functional blocks. Key optimizations include the reuse of hardware designed for prior generation V̂6 and VP7 decoders. In order to reduce implementation complexity, cost and power consumption, a non exact, approximate deblocking loop filter is implemented.

公开(公告)号：US09648350B2

公开(公告)日：2017-05-09

申请号：US14335099

申请日：2014-07-18

Applicant: Texas Instruments Incorporated

Inventor： Mihir Narendra Mody ,  Vipul Paladiya ,  Kapil Ahuja

IPC: G06K9/36 ,  H04N19/625 ,  H04N19/44 ,  H04N19/34

CPC classification number: H04N19/44 ,  H04N19/124 ,  H04N19/34 ,  H04N19/423 ,  H04N19/625 ,  H04N19/70

Abstract: A progressive JPEG (joint photographic experts group) decoder is disclosed. The progressive JPEG decoder includes a processing unit that receives a plurality of progressive scans and generates a plurality of modified progressive scans (MPSs). A baseline JPEG decoder, coupled to the processing unit, includes a Huffman decoder, an inverse quantization unit and an inverse transform unit. The Huffman decoder receives a current MPS and generates a set of transform coefficients corresponding to the current MPS. The processing unit adds a set of transform coefficients corresponding to a previous MPS to the set of transform coefficients corresponding to the current MPS, and the processing unit generates quantization indices. The inverse quantization unit estimates inverse quantization values based on the quantization indices. The inverse transform unit estimates inverse transform decoded values based on the estimated inverse quantization values and generates a set of pixels corresponding to the current MPS.

公开(公告)号：US20150296212A1

公开(公告)日：2015-10-15

申请号：US14684334

申请日：2015-04-11

Applicant: Texas Instruments Incorporated

Inventor： Dipan Kumar Mandal ,  Mihir Narendra Mody ,  Mahesh Madhukar Mehendale ,  Chaitanya Satish Ghone ,  Piyali Goswami ,  Naresh Kumar Yadav ,  Hetul Sanghvi ,  Niraj Nandan

IPC: H04N19/42 ,  G06F9/30 ,  H04N19/463 ,  G06F9/38

CPC classification number: H04N19/42 ,  G06F9/30181 ,  G06F9/3885 ,  H04N19/43 ,  H04N19/463

Abstract: A control processor for a video encode-decode engine is provided that includes an instruction pipeline. The instruction pipeline includes an instruction fetch stage coupled to an instruction memory to fetch instructions, an instruction decoding stage coupled to the instruction fetch stage to receive the fetched instructions, and an execution stage coupled to the instruction decoding stage to receive and execute decoded instructions. The instruction decoding stage and the instruction execution stage are configured to decode and execute a set of instructions in an instruction set of the control processor that are designed specifically for accelerating video sequence encoding and encoded video bit stream decoding.

Abstract translation: 提供了一种用于视频编码解码引擎的控制处理器，其包括指令流水线。 指令流水线包括与指令存储器耦合以取指令的指令提取级，耦合到指令提取级以接收所取指令的指令解码级，以及耦合到指令解码级的接收和执行解码指令的执行级。 指令解码级和指令执行级被配置为解码和执行专门用于加速视频序列编码和编码视频位流解码的控制处理器的指令集中的一组指令。

公开(公告)号：US09078001B2

公开(公告)日：2015-07-07

申请号：US13920238

申请日：2013-06-18

Applicant: Texas Instruments Incorporated

Inventor： Mihir Narendra Mody ,  Dinesh Kothandapani

IPC: G06K9/36 ,  H04N19/44 ,  H04N19/436 ,  G06K9/46

CPC classification number: H04N19/44 ,  H04N19/436

Abstract: A bitplane decoding system where the bitplane operations are broken up into an optimized plurality of sub-tasks. A pipeline structure is established for the execution of said sub-tasks on a plurality of processors or dedicated hardware logic blocks in a manner that allows efficient execution of the sub-tasks in parallel across two processors, resulting in a significant increase in performance.

Abstract translation: 位平面解码系统，其中位平面操作被分解成优化的多个子任务。 为了在多个处理器或专用硬件逻辑块上执行所述子任务建立流水线结构，其允许跨两个处理器并行地执行子任务的高效执行，导致性能显着提高。

公开(公告)号：US20150036738A1

公开(公告)日：2015-02-05

申请号：US14447062

申请日：2014-07-30

Applicant: Texas Instruments Incorporated

Inventor： Hrushikesh Tukaram Garud ,  Mihir Narendra Mody ,  Soyeb Nagori

IPC: H04N19/147 ,  H04N19/182 ,  H04N19/86 ,  H04N19/117

CPC classification number: H04N19/147 ,  H04N19/117 ,  H04N19/149 ,  H04N19/176 ,  H04N19/182 ,  H04N19/82

Abstract: The disclosure provides a sample adaptive offset (SAO) encoder. The SAO encoder includes a statistics collection (SC) block and a rate distortion optimization (RDO) block coupled to the SC block. The SC block receives a set of deblocked pixels and a set of original pixels. The SC block categorizes each deblocked pixel of the set of deblocked pixels in at least one of a plurality of band and edge categories. The SC block estimates an error in each category as difference between a deblocked pixel of the set of deblocked pixels and corresponding original pixel of the set of original pixels. The RDO block determines a set of candidate offsets associated with each category and selects a candidate offset with a minimum RD cost. The minimum RD cost is used by a SAO type block and a decision block to generate final offsets for the SAO encoder.

Abstract translation: 本公开提供了一种采样自适应偏移（SAO）编码器。 SAO编码器包括统计收集（SC）块和耦合到SC块的速率失真优化（RDO）块。 SC块接收一组去块像素和一组原始像素。 SC块将多个带和边缘类别中的至少一个中的去块像素组的每个解块像素进行分类。 SC块将每个类别中的误差估计为该组去块像素的解块像素与该原始像素组中相应的原始像素之间的差。 RDO块确定与每个类别相关联的候选偏移集合，并且选择具有最小RD成本的候选偏移量。 最小RD成本由SAO类型块和决策块用于生成SAO编码器的最终偏移量。