公开(公告)号：US20220190184A1

公开(公告)日：2022-06-16

申请号：US17546503

申请日：2021-12-09

Applicant: STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics (Research & Development) Limited

Inventor： Denis RIDEAU ,  Dominique GOLANSKI ,  Alexandre LOPEZ ,  Gabriel MUGNY

IPC: H01L31/107 ,  H01L31/18

Abstract: A single photon avalanche diode (SPAD) includes a PN junction in a semiconductor well doped with a first type of dopant. The PN junction is formed between a first region doped with the first type of dopant and a second region doped with a second type of dopant opposite to the first type of dopant. The first doped region is shaped so as to incorporate local variations in concentration of dopants that are configured, in response to a voltage between the second doped region and the semiconductor well that is greater than or equal to a level of a breakdown voltage of the PN junction, to generate a monotonic variation in the electrostatic potential between the first doped region and the semiconductor well.

公开(公告)号：US20220178989A1

公开(公告)日：2022-06-09

申请号：US17543337

申请日：2021-12-06

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Alexandre AYRES ,  Bertrand BOROT

IPC: G01R31/28

Abstract: An integrated circuit chip is attached to a support that includes first conductive elements. First conductive pads are located on the integrated circuit chip and are electrically coupled to the first conductive elements by conductive wires. The integrated circuit chip further includes a conductive track. A switch circuit is provided to selectively electrically connect each first conductive pad to the conductive track. To test the conductive wires, a group of first conductive pads are connected by their respective switch circuits to the conductive track and current flow between corresponding first conductive elements is measured.

公开(公告)号：US20220155144A1

公开(公告)日：2022-05-19

申请号：US17569171

申请日：2022-01-05

Applicant: STMicroelectronics (Research & Development) Limited ,  STMicroelectronics (Grenoble 2) SAS ,  STMicroelectronics (Crolles 2) SAS

Inventor： Pierre MALINGE ,  Frédéric LALANNE ,  Jeffrey M. RAYNOR ,  Nicolas MOENECLAEY

IPC: G01J1/42 ,  H05B47/105 ,  H04N5/353 ,  G09G3/3225

Abstract: In an embodiment a method for measuring ambient light includes successively synchronizing optical signal acquisition phases with extinction phases of a disruptive light source, wherein the disruptive light source periodically provides illumination phases and the extinction phases, accumulating, in each acquisition phase, photo-generated charges by at least one photosensitive pixel comprising a pinned photodiode, wherein an area of the pinned photodiode is less than or equal to 1/10 of an area of the at least one photosensitive pixel, transferring, for each pixel, the accumulated photo-generated charges to a sensing node, converting, for each pixel, the transferred charges to a voltage at a voltage node and converting, for each pixel, the transferred charges to a digital number

公开(公告)号：US20220085084A1

公开(公告)日：2022-03-17

申请号：US17471049

申请日：2021-09-09

Applicant: STMICROELECTRONICS (RESEARCH & DEVELOPMENT) LIMITED ,  STMicroelectronics (Crolles 2) SAS

Inventor： Raul Andres BIANCHI ,  Marios BARLAS ,  Alexandre LOPEZ ,  Bastien MAMDY ,  Bruce RAE ,  Isobel NICHOLSON

IPC: H01L27/146

Abstract: The present disclosure relates to a pixel comprising: a photodiode comprising a portion of a substrate of a semiconductor material, extending vertically from a first face of the substrate to a second face of the substrate configured to receive light; a layer of a first material covering each of the lateral surfaces of the portion; a layer of a second material covering the portion on the side of the first face, first and second material having refractive indexes lower than that of the semiconductor material; and a diffractive structure disposed on a face of the photodiode on the side of the second face.

公开(公告)号：US11269141B2

公开(公告)日：2022-03-08

申请号：US16821370

申请日：2020-03-17

Applicant: STMicroelectronics S.r.l. ,  STMicroelectronics (Crolles 2) SAS

Inventor： Frédéric Boeuf ,  Luca Maggi

IPC: G02B6/124 ,  G02B6/34 ,  G02B6/43 ,  G02B6/30 ,  G02B6/12 ,  G02B6/136

Abstract: A photonic integrated circuit chip includes vertical grating couplers defined in a first layer. Second insulating layers overlie the vertical grating coupler and an interconnection structure with metal levels is embedded in the second insulating layers. A cavity extends in depth through the second insulating layers all the way to an intermediate level between the couplers and the metal level closest to the couplers. The cavity has lateral dimensions such that the cavity is capable of receiving a block for holding an array of optical fibers intended to be optically coupled to the couplers.

公开(公告)号：US11258148B2

公开(公告)日：2022-02-22

申请号：US16901832

申请日：2020-06-15

Applicant: STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics SA

Inventor： Victor Fiorese ,  Frederic Gianesello ,  Florian Voineau

IPC: H01P1/161 ,  H01P1/213 ,  H01P5/19 ,  H01Q25/00

Abstract: An orthomode junction for separating and/or combining orthogonally-polarized radiofrequency wave signals, comprises a body which has a main cavity forming a main waveguide, which has a blind end, and auxiliary cavities forming auxiliary waveguides, which communicate laterally with the main cavity in the vicinity of the blind end thereof, and a deflection insert situated at the blind end of the main cavity and facing the auxiliary cavities, the deflection insert having different shapes on the side of the auxiliary cavities respectively.

公开(公告)号：US11251084B2

公开(公告)日：2022-02-15

申请号：US16909378

申请日：2020-06-23

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Pascal Chevalier ,  Alexis Gauthier ,  Gregory Avenier

IPC: H01L21/8222 ,  H01L21/265 ,  H01L27/06 ,  H01L29/06 ,  H01L29/66 ,  H01L29/737 ,  H01L29/93

Abstract: At least one bipolar transistor and at least one variable capacitance diode are jointly produced by a method on a common substrate.

公开(公告)号：US11249133B2

公开(公告)日：2022-02-15

申请号：US16745813

申请日：2020-01-17

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Yann Carminati

IPC: G01R31/28 ,  G01R31/3183 ,  G01R31/319 ,  G01R31/30 ,  G08C15/04 ,  G05B11/01

Abstract: A value representative of a dispersion of a propagation delay of assemblies of electronic components is determined. A component test structure includes stages of components and a logic circuit connected in a ring. Each stage includes two assemblies of similar components configured to conduct a signal. A test device is configured to obtain values of the component test structure and to perform operations on these values.

公开(公告)号：US11231548B2

公开(公告)日：2022-01-25

申请号：US16847189

申请日：2020-04-13

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Frederic Boeuf ,  Charles Baudot

IPC: G02B6/12 ,  G02B6/27 ,  G02B6/30 ,  G02B6/124 ,  G02B6/122 ,  G02B6/126 ,  G02B6/34 ,  G02B6/42

Abstract: A three-dimensional photonic integrated structure includes a first semiconductor substrate and a second semiconductor substrate. The first substrate incorporates a first waveguide and the second semiconductor substrate incorporates a second waveguide. An intermediate region located between the two substrates is formed by a one dielectric layer. The second substrate further includes an optical coupler configured for receiving a light signal. The first substrate and dielectric layer form a reflective element located below and opposite the grating coupler in order to reflect at least one part of the light signal.

公开(公告)号：US20220011479A1

公开(公告)日：2022-01-13

申请号：US17482237

申请日：2021-09-22

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Vincent FARYS ,  Alain INARD ,  Olivier NOBLANC

IPC: G02B5/02 ,  C23C16/34 ,  C23C16/56 ,  C23C18/12

Abstract: Methods of manufacture of an optical diffuser. In one embodiment, an optical diffuser is formed by providing a wafer including a silicon slice of which an upper face is covered with a first layer made of a first material itself covered with a second layer made of a second selectively etchable material with respect to the first material. The method further includes forming openings in the second layer extending up to the first layer and filling the openings in the second layer with a third material. The method yet further includes bonding a glass substrate to the wafer on the side of its upper face and removing the silicon slice.